The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Jong-Jiann Shieh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. You-Jan Tsai, Jong-Jiann Shieh
    Speculative Issue Logic. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:323-335 [Conf]
  2. Tzung-Rei Yang, Jong-Jiann Shieh
    Dynamic Fetch Engine for Simultaneous Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:489-502 [Conf]
  3. Zheng-Kuo Wu, Jong-Jiann Shieh
    Block Based Fetch Engine for Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    CAINE, 2002, pp:201-204 [Conf]
  4. Feng-Jiann Shiao, Jong-Jiann Shieh
    An Issue Logic for Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    CAINE, 2003, pp:268-271 [Conf]
  5. Jong-Jiann Shieh, Christos A. Papachristou
    On reordering instruction streams for pipelined computers. [Citation Graph (0, 0)][DBLP]
    MICRO, 1989, pp:199-206 [Conf]
  6. Jong-Jiann Shieh, Christos A. Papachristou
    An instruction reoderer for pipelined computers. [Citation Graph (0, 0)][DBLP]
    MICRO, 1990, pp:135-142 [Conf]
  7. Yung-Chung Wu, Jong-Jiann Shieh
    A Multiple Blocks Fetch Engine for High Performance Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2001, pp:339-344 [Conf]

  8. Power Improvement Using Block-Based Loop Buffer with Innermost Loop Control. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002