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Takao Onoye: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroshi Tsutsui, Takahiko Masuzaki, Yoshiteru Hayashi, Yoshitaka Taki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Scalable Design Framework for JPEG2000 System Architecture. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:296-308 [Conf]
  2. Makoto Furuie, Bao-Yu Song, Yukihiro Yoshida, Takao Onoye, Isao Shirakawa
    Layout generation of array cell for NMOS 4-phase dynamic logic (short paper). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:529-532 [Conf]
  3. Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
    A dynamically reconfigurable hardware-based cipher chip. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:11-12 [Conf]
  4. Roberto Y. Omaki, Yu Dong, Morgan Hirosuke Miki, Makoto Furuie, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa
    Realtime wavelet video coder based on reduced memory accessing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:15-16 [Conf]
  5. Takao Onoye, Gen Fujita, Hiroyuki Okuhata, Morgan Hirosuke Miki, Isao Shirakawa
    Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:589-594 [Conf]
  6. Kyoko Ueda, Atsushi Kosaka, Ryoichi Watanabe, Yoshinori Takeuchi, Takao Onoye, Yuichi Itoh, Yoshifumi Kitamura, Fumio Kishino
    m-ActiveCube; Multimedia Extension of Spatial Tangible User Interface. [Citation Graph (0, 0)][DBLP]
    BioADIT, 2006, pp:363-370 [Conf]
  7. Atsushi Kosaka, Satoshi Yamaguchi, Hiroyuki Okuhata, Takao Onoye, Isao Shirakawa
    SoC design of Ogg Vorbis decoder using embedded processor. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:481-487 [Conf]
  8. Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Y. Meng
    FeRAM Circuit Technology for System on a Chip. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 1999, pp:193-0 [Conf]
  9. Kosuke Tsujino, Atsuhito Shigiya, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura, Wataru Kobayashi
    A DSP-Based 3-D Sound Synthesis System for Moving Sound Images. [Citation Graph (0, 0)][DBLP]
    GAME-ON, 2003, pp:23-0 [Conf]
  10. Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye
    A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:47-53 [Conf]
  11. Kenji Hontani, Takaaki Imanaka, Gen Fujita, Takao Onoye, Isao Shirakawa
    Real-time face object extraction for video phone. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2003, pp:873-876 [Conf]
  12. Yu Dong, Roberto Y. Omaki, Takao Onoye, Isao Shirakawa
    VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  13. Hiroshi Tsutsui, Takahiko Masuzaki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Adaptive rate control for JPEG2000 image coding in embedded systems. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2002, pp:77-80 [Conf]
  14. Morgan Hirosuke Miki, Motoki Kimura, Takao Onoye, Isao Shirakawa
    High Performance Java Hardware Engine and Software Kernel for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:109-120 [Conf]
  15. Yoshiteru Hayashi, Hiroshi Tsutsui, Takahiko Masuzaki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Design framework for JPEG2000 encoding system architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:740-743 [Conf]
  16. S. Komata, A. Pal, Noriaki Sakamoto, Wataru Kobayashi, Takao Onoye, Isao Shirakawa
    Interactive interface of realtime 3D sound movement for embedded applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:520-523 [Conf]
  17. T. Matsumura, N. Iwanaga, Takao Onoye, Wataru Kobayashi, Isao Shirakawa, Itthichai Arungsrisangchai
    3D sound movement system for embedded applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5345-5348 [Conf]
  18. Ryusuke Miyamoto, Hiroaki Sugita, Yoshiteru Hayashi, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Yukihiro Nakamura
    High quality Motion JPEG2000 coding scheme based on the human visual system. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2096-2099 [Conf]
  19. Takayuki Sagishima, Kozo Kimura, Hiroaki Hirata, Tokuzo Kiyohara, Shigeo Asahara, Takao Onoye, Isao Shirakawa
    Multi-Threaded Processor for Image Generation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:231-234 [Conf]
  20. Hiroaki Sugita, Minh Q. Minh, Takahiko Masuzaki, Hiroshi Tsutsui, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    JPEG2000 high-speed progressive decoding scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:873-876 [Conf]
  21. Keishi Chikamura, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    IEEE1394 system simulation environment and a design of its link layer controller. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:1-4 [Conf]
  22. Hiroshi Tsutsui, K. Hiwada, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    A design of LUT-array-based PLD and a synthesis approach based on sum of generalized complex terms expression. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:203-206 [Conf]
  23. Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
    VLSI architecture of dynamically reconfigurable hardware-based cipher. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:734-737 [Conf]
  24. Morgan Hirosuke Miki, Daisuke Taki, Gen Fujita, Takao Onoye, Isao Shirakawa, T. Fujiwara, T. Kasami
    Recursive maximum likelihood decoder for high-speed satellite communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:572-575 [Conf]
  25. H. Fujishima, Y. Takemoto, T. Yoneda, Takao Onoye, Isao Shirakawa
    Hybrid media-processor core for natural and synthetic video decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:275-278 [Conf]
  26. Yoshihiro Uchida, M. Ise, Takao Onoye, Isao Shirakawa, Itthichai Arungsrisangchai
    VLSI architecture of digital matched filter and prime interleaver for W-CDMA. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:269-272 [Conf]
  27. Takahiko Masuzaki, Hiroshi Tsutsui, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    JPEG2000 adaptive rate control for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:333-336 [Conf]
  28. Morgan Hirosuke Miki, Gen Fujita, Takao Onoye, Isao Shirakawa
    Low-power H.263 video CoDec dedicated to mobile computing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:80-83 [Conf]
  29. Yukihiro Yoshida, Bao-Yu Song, Hiroyuki Okuhata, Takao Onoye, Isao Shirakawa
    An object code compression approach to embedded processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:265-268 [Conf]
  30. Kenichi Shinkai, Masanori Hashimoto, Takao Onoye
    Future Prediction of Self-Heating in Short Intra-Block Wires. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:660-665 [Conf]
  31. Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto
    System-Level Design of IEEE1394 Bus Segment Bridge. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:74-79 [Conf]
  32. T. Kaya, Isao Shirakawa, Ryusuke Miyamoto, Takao Onoye
    Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:- [Conf]
  33. Noriaki Sakamoto, Wataru Kobayashi, Takao Onoye, Isao Shirakawa
    Single DSP Implementation of Realtime 3D Sound Synthesis Algorithm. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:1, pp:55-74 [Journal]
  34. Jumpei Ashida, Ryusuke Miyamoto, Hiroshi Tsutsui, Takao Onoye, Yukihiro Nakamura
    Probabilistic Pedestrian Tracking Based on a Skeleton Model. [Citation Graph (0, 0)][DBLP]
    ICIP, 2006, pp:2825-2828 [Conf]
  35. Hiroki Sugano, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura
    Efficient memory architecture for JPEG2000 entropy codec. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  36. M. N. Bin Mohd Nor, T. Matsumura, Takao Onoye
    Direction of arrival estimation improvement of speech on a two-microphone array. [Citation Graph (0, 0)][DBLP]
    SIP, 2007, pp:122-127 [Conf]

  37. Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. [Citation Graph (, )][DBLP]

  38. Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. [Citation Graph (, )][DBLP]

  39. Coarse-grained dynamically reconfigurable architecture with flexible reliability. [Citation Graph (, )][DBLP]

  40. Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. [Citation Graph (, )][DBLP]

  41. Clock skew reduction by self-compensating manufacturing variability with on-chip sensors. [Citation Graph (, )][DBLP]

  42. Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. [Citation Graph (, )][DBLP]

  43. Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. [Citation Graph (, )][DBLP]

  44. Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. [Citation Graph (, )][DBLP]

  45. Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. [Citation Graph (, )][DBLP]

  46. Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. [Citation Graph (, )][DBLP]

  47. Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. [Citation Graph (, )][DBLP]

  48. Embedded implementation of acoustic field enhancement for stereo headphones. [Citation Graph (, )][DBLP]

  49. Realtime face object extraction algorithm for video phone. [Citation Graph (, )][DBLP]

  50. High speed JPEG2000 encoder by configurable processor. [Citation Graph (, )][DBLP]

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