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Lucian N. Vintan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lucian N. Vintan, Arpad Gellert, Adrian Florea, Marius Oancea, Colin Egan
    Understanding Prediction Limits Through Unbiased Branches. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:480-487 [Conf]
  2. Colin Egan, Gordon Steven, Lucian N. Vintan
    Cached Two-Level Adaptive Branch Predictors with Multiple Stages. [Citation Graph (0, 0)][DBLP]
    ARCS, 2002, pp:179-194 [Conf]
  3. Colin Egan, Gordon Steven, Won Shim, Lucian N. Vintan
    Applying Caching to Two-Level Adaptive Branch Prediction. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:186-193 [Conf]
  4. Gordon B. Steven, Rubén Anguera, Colin Egan, Fleur Steven, Lucian N. Vintan
    Dynamic Branch Prediction Using Neural Networks. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:178-185 [Conf]
  5. Lucian N. Vintan, Colin Egan
    Extending Correlation in Branch Prediction Schemes. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1441-1448 [Conf]
  6. Colin Egan, Gordon Steven, Patrick Quick, Rubén Anguera, Fleur Steven, Lucian N. Vintan
    Two-level branch prediction using neural networks. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:557-570 [Journal]
  7. Lucian N. Vintan, Marius Sbera, Ioan Z. Mihu, Adrian Florea
    An alternative to branch prediction: pre-computed branches. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2003, v:31, n:3, pp:20-29 [Journal]
  8. Arpad Gellert, Adrian Florea, Maria Vintan, Colin Egan, Lucian N. Vintan
    Unbiased Branches: An Open Problem. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:16-27 [Conf]
  9. Michael F. P. O'Boyle, François Bodin, José González, Lucian N. Vintan
    Topic 4 High-Performance Architectures and Compilers. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2007, pp:235- [Conf]

  10. Energy-performance design space exploration in SMT architectures exploiting selective load value predictions. [Citation Graph (, )][DBLP]


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