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Pierre Bomel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin
    Memory accesses management during high level synthesis. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:42-47 [Conf]
  2. Pierre Bomel, Eric Martin, Emmanuel Boutillon
    Synchronization Processor Synthesis for Latency Insensitive Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:896-897 [Conf]
  3. Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, A.-M. Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno
    Hardware Virtual Components Compliant with Communication System Standards. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:88-95 [Conf]
  4. Pierre Bomel, Nabil Abdelli, Eric Martin, A.-M. Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
    High-Level Synthesis in Latency Insensitive System Methodology. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:96-101 [Conf]
  5. Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin
    High-level synthesis under I/O timing and memory constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:680-683 [Conf]
  6. Pierre Bomel, Nabil Abdelli, Eric Martin, A.-M. Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
    DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:424-433 [Conf]
  7. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
    Constrained algorithmic IP design for system-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:94-105 [Journal]
  8. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
    A formal method for hardware IP design and integration under I/O and timing constraints. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:29-53 [Journal]
  9. Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
    High-level synthesis under I/O Timing and Memory constraints [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  10. Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin
    Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  11. Pierre Bomel, Eric Martin, Emmanuel Boutillon
    Synchronization Processor Synthesis for Latency Insensitive Systems [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  12. Ultra-Fast Downloading of Partial Bitstreams through Ethernet. [Citation Graph (, )][DBLP]


  13. Networked Self-adaptive Systems: An Opportunity for Configuring in the Large. [Citation Graph (, )][DBLP]


  14. Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems. [Citation Graph (, )][DBLP]


  15. A Networked, Lightweight and Partially Reconfigurable Platform. [Citation Graph (, )][DBLP]


  16. Hardware Discrete Channel Emulator. [Citation Graph (, )][DBLP]


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