Search the dblp DataBase

Publications of Author

1. Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin
   Memory accesses management during high level synthesis. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2004, pp:42-47 [Conf]
   
2. Johann Laurent, Nathalie Julien, Eric Senn, Eric Martin
   Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:666-667 [Conf]
   
3. David Elléouet, Nathalie Julien, Dominique Houzet, J.-G. Cousin, Eric Martin
   Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. [Citation Graph (0, 0)][DBLP]
   DSD, 2004, pp:394-401 [Conf]
   
4. Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
   Memory Aware HLS and the Implementation of Ageing Vectors. [Citation Graph (0, 0)][DBLP]
   DSD, 2004, pp:88-95 [Conf]
   
5. Florian Marteil, Nathalie Julien, Eric Senn, Eric Martin
   A Complete Methodology for Memory Optimization in DSP Applications. [Citation Graph (0, 0)][DBLP]
   DSD, 2004, pp:98-103 [Conf]
   
6. Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
   A memory aware behavioral synthesis tool for real-time VLSI circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2004, pp:82-85 [Conf]
   
7. S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin
   Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1999, pp:334-335 [Conf]
   
8. S. Gailhard, Nathalie Julien, Jean-Philippe Diguet, Eric Martin
   How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1998, pp:426-0 [Conf]
   
9. David Elléouet, Nathalie Julien, Dominique Houzet
   A high level SoC power estimation based on IP modeling. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
10. Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin
    Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:354-360 [Conf]
    
11. Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
    A Memory Aware High Level Synthesis Tool . [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:279-280 [Conf]
    
12. David Elléouet, Yannig Savary, Nathalie Julien
    An FPGA Power Aware Design Flow. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:415-424 [Conf]
    
13. Eric Senn, Nathalie Julien, Johann Laurent, Eric Martin
    Power Consumption Estimation of a C Program for Data-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:332-341 [Conf]
    
14. Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin
    SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:342-351 [Conf]
    
15. Nathalie Julien, Johann Laurent, Eric Senn, David Elléouet, Yannig Savary, Nabil Abdelli, J. Ktari
    Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:137-142 [Conf]
    
16. Eric Senn, Nathalie Julien, David Elléouet, Yannig Savary, Nabil Abdelli
    Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:83-90 [Conf]
    
17. Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin
    Power Consumption Modeling and Characterization of the TI C6201. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:40-49 [Journal]
    
18. Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
    Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
    
19. Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
    A Memory Aware High Level Synthesis Too [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
    
20. Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
    Memory Aware High-Level Synthesis for Embedded Systems [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
    
21. 
    Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors. [Citation Graph (, )][DBLP]
    
    
22. 
    Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses. [Citation Graph (, )][DBLP]