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Fabio Salice: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alberto Allara, S. Filipponi, Fabio Salice, William Fornaciari, Donatella Sciuto
    A Flexible Model for Evaluating the Behavior of Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:109-114 [Conf]
  2. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Energy estimation for 32-bit microprocessors. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:24-28 [Conf]
  3. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Source-level execution time estimation of C programs. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:98-103 [Conf]
  4. William Fornaciari, Fabio Salice, Umberto Bondi, Edi Magini
    Development cost and size estimation starting from high-level specifications. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:86-91 [Conf]
  5. William Fornaciari, Fabio Salice, Daniele Paolo Scarpazza
    Early estimation of the size of VHDL projects. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:207-212 [Conf]
  6. Donatella Sciuto, Fabio Salice, Luigi Pomante, William Fornaciari
    Metrics for design space exploration of heterogeneous multiprocessor embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:55-60 [Conf]
  7. Carlo Brandolese, William Fornaciari, Fabio Salice
    An area estimation methodology for FPGA based designs at systemc-level. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:129-132 [Conf]
  8. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    An instruction-level functionally-based energy estimation model for 32-bits microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:346-351 [Conf]
  9. Alberto Allara, William Fornaciari, Fabio Salice, Donatella Sciuto
    A Model for System-Level Timed Analysis and Profiling. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:204-210 [Conf]
  10. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Library Functions Timing Characterization for Source-Level Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11132-11133 [Conf]
  11. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Analysis and Modeling of Energy Reducing Source Code Transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:306-311 [Conf]
  12. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Fault Analysis in Networks with Concurrent Error Detection Properties. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:957-958 [Conf]
  13. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Specification for Self-Checking Data-Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1278-1283 [Conf]
  14. William Fornaciari, P. Micheli, Fabio Salice, L. Zampella
    A First Step Towards Hw/Sw Partitioning of UML Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10668-10673 [Conf]
  15. Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto
    A model of soft error effects in generic IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:334-342 [Conf]
  16. Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Co-Design: The FIR Case Study. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:433-441 [Conf]
  17. Cristiana Bolchini, Luigi Pomante, Donatella Sciuto, Fabio Salice
    A Synthesis Methodology Aimed at Improving the Quality of TSC Devices. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:247-255 [Conf]
  18. Cristiana Bolchini, Fabio Salice
    A Software Methodology for Detecting Hardware Faults in VLIW Data Paths. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:170-175 [Conf]
  19. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Designing Self-Checking FPGAs through Error Detection Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:60-68 [Conf]
  20. Cristiana Bolchini, Donatella Sciuto, Fabio Salice
    Designing Networks with Error Detection Properties through the Fault-Error Relation. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:290-297 [Conf]
  21. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, R. Zavaglia
    An Integrated Design Approach for Self-Checking FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:443-450 [Conf]
  22. A. Dell'Acqua, M. Hansen, S. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, A. Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, S. Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson
    System Level Policies for Fault Tolerance Issues in the FERMI Project. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:1-8 [Conf]
  23. Fabio Salice, Mariagiovanna Sami, Renato Stefanelli
    Fault-Tolerant CAM Architectures: A Design Framework. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:233-244 [Conf]
  24. Fabio Salice, Mariagiovanna Sami, Donatella Sciuto
    Synthesis of Multi-level Self-Checking Logic. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:115-123 [Conf]
  25. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:32-0 [Conf]
  26. Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni
    An Assembly-Level Execution-Time Model for Pipelined Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:195-200 [Conf]
  27. Cristiana Bolchini, Donatella Sciuto, Fabio Salice
    A TSC Evaluation Function for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:555-560 [Conf]
  28. Alberto Allara, S. Filipponi, William Fornaciari, Fabio Salice, Donatella Sciuto
    Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:400-405 [Conf]
  29. Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
    Reliability Properties Assessment at System Level: A Co-design Framework. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:165-171 [Conf]
  30. Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
    A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:32-0 [Conf]
  31. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Designing Reliable Embedded Systems Based on 32 Bit Microprocessors. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:137- [Conf]
  32. Cristiana Bolchini, Franco Fummi, R. Gemelli, Fabio Salice
    A BDD Based Algorithm for Detecting Difficult Faults. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2015-2018 [Conf]
  33. Giacomo Buonanno, Fabio Salice, Donatella Sciuto
    Behavior of Self-Checking Checkers for 1-out-of-3 Codes Based on Pass-Transistor Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1924-1927 [Conf]
  34. William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame
    Modeling Assembly Instruction Timing in Superscalar Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:132-137 [Conf]
  35. Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni
    Dynamic modeling of inter-instruction effects for execution time estimation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:136-141 [Conf]
  36. Cristiana Bolchini, William Fornaciari, Fabio Salice, Donatella Sciuto
    Concurrent Error Detection at Architectural Level. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:72-75 [Conf]
  37. Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
    On-line fault detection in a hardware/software co-design environment. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:51-56 [Conf]
  38. Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, Donatella Sciuto
    A Multi-Level Strategy for Software Power Estimation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:187-192 [Conf]
  39. Carlo Brandolese, William Fornaciari, Fabio Salice
    Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:238-247 [Conf]
  40. Fabio Salice, William Fornaciari, Luca Del Vecchio, Luigi Pomante
    Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:661-665 [Conf]
  41. Cristiana Bolchini, Fabio Salice, Fabio A. Schreiber, Letizia Tanca
    Physical and Logical Data Structures for Very Small Databases. [Citation Graph (0, 0)][DBLP]
    SEBD, 2002, pp:337-344 [Conf]
  42. Alberto Allara, Massimo Bombana, William Fornaciari, Fabio Salice
    A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:60-72 [Journal]
  43. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Fault Analysis for Networks with Concurrent Error Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:66-74 [Journal]
  44. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    The Impact of Source Code Transformations on Software Power and Energy Consumption. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:5, pp:477-502 [Journal]
  45. Cristiana Bolchini, Paolo Ferrandi, Pier Luca Lanzi, Fabio Salice
    Evolving classifiers on field programmable gate arrays: Migrating XCS to FPGAs. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2006, v:52, n:8-9, pp:516-533 [Journal]
  46. Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, Donatella Sciuto
    Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:5, pp:508-519 [Journal]
  47. Carlo Brandolese, Fabio Salice, William Fornaciari, Donatella Sciuto
    Static power modeling of 32-bit microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1306-1316 [Journal]
  48. Cristiana Bolchini, Fabio Salice, Fabio A. Schreiber, Letizia Tanca
    Logical and physical design issues for smart card databases. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Inf. Syst., 2003, v:21, n:3, pp:254-285 [Journal]
  49. Cristiana Bolchini, Paolo Ferrandi, Pier Luca Lanzi, Fabio Salice
    Toward an FPGA implementation of XCS. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:2053-2060 [Conf]
  50. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Specification for Self-Checking Data-Paths [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  51. William Fornaciari, Fabio Salice
    A new architecture for the automatic design of custom digital neural network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:4, pp:502-506 [Journal]
  52. Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto
    Design of VHDL-based totally self-checking finite-state machine and data-path descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:98-103 [Journal]

  53. A performance-oriented hardware/software partitioning for datapath applications. [Citation Graph (, )][DBLP]


  54. A novel methodology for designing TSC networks based on the parity bit code. [Citation Graph (, )][DBLP]


  55. RAM-Based Fault Tolerant State Machines for FPGAs. [Citation Graph (, )][DBLP]


  56. A Generalized Approach for the Use of Convolutional Coding in SEU Mitigation. [Citation Graph (, )][DBLP]


  57. An Incremental Approach to Functional Diagnosis. [Citation Graph (, )][DBLP]


  58. A New Framework for Design and Simulation of Complex Hardware/Software Systems. [Citation Graph (, )][DBLP]


  59. Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs. [Citation Graph (, )][DBLP]


  60. An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System. [Citation Graph (, )][DBLP]


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