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Divya Arora:
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- Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Enhancing security through hardware-assisted run-time validation of program data properties. [Citation Graph (0, 0)][DBLP] CODES+ISSS, 2005, pp:190-195 [Conf]
- Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Architectural support for safe software execution on embedded processors. [Citation Graph (0, 0)][DBLP] CODES+ISSS, 2006, pp:106-111 [Conf]
- Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. [Citation Graph (0, 0)][DBLP] DAC, 2006, pp:496-501 [Conf]
- Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. [Citation Graph (0, 0)][DBLP] DATE, 2005, pp:178-183 [Conf]
- Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1295-1308 [Journal]
- Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Architectural Support for Run-Time Validation of Program Data Properties. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:546-559 [Journal]
- Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:699-710 [Journal]
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