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Reinaldo A. Bergamaschi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Reinaldo A. Bergamaschi, Grant Martin
    System-level design tools: who needs them, who has them, and how much should they cost? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:79-80 [Conf]
  2. Reinaldo A. Bergamaschi, Grant Martin, Wayne Wolf, Rolf Ernst, Kees A. Vissers, Jack Kouloheris
    The future of system-level design: can we find the right solutions to the right problems at the right time? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:231- [Conf]
  3. Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal
    SEAS: a system for early analysis of SoCs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:150-155 [Conf]
  4. Francine Bacchini, Pierre G. Paulin, Reinaldo A. Bergamaschi, Raj Pawate, Arie Bernstein, Ramesh Chandra, Mohamed Ben-Romdhane
    System level design: six success stories in search of an industry. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:349-350 [Conf]
  5. Reinaldo A. Bergamaschi
    Productivity Issues in High-Level Design: Are Tools Solving the Real Problems? [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:674-677 [Conf]
  6. Reinaldo A. Bergamaschi
    Behavioral Network Graph: Unifying the Domains of High-Level and Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:213-218 [Conf]
  7. Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
    Data-Path Synthesis Using Path Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:591-596 [Conf]
  8. Reinaldo A. Bergamaschi, Yunjian Jiang
    State-based power analysis for systems-on-chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:638-641 [Conf]
  9. Reinaldo A. Bergamaschi, William R. Lee
    Designing systems-on-chip using cores. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:420-425 [Conf]
  10. Reinaldo A. Bergamaschi, Donald Lobo, Andreas Kuehlmann
    Control Optimization in High-Level Synthesis Using Behavioral Don't Cares. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:657-661 [Conf]
  11. Raul Compasano, Reinaldo A. Bergamaschi
    Synthesis Using Path-Based scheduling: algorithms and Exercises. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:450-455 [Conf]
  12. Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi
    Heterogeneous behavioral hierarchy for system level designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:565-570 [Conf]
  13. Wolfgang Rosenstiel, Reinaldo A. Bergamaschi, Frank Ghenassia, Thorsten Groetker, Masamichi Kawarabayashi, Marinus C. van Lier, Albrecht Mayer, Mike Meredith, Mark Milligan, Stuart Swan
    Is there a Market for SystemC Tools? [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:950- [Conf]
  14. Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi
    Modeling and Integration of Peripheral Devices in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10136-10141 [Conf]
  15. Reinaldo A. Bergamaschi
    The Effects of False Paths in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:80-83 [Conf]
  16. Reinaldo A. Bergamaschi, Brian M. Barry, John Duimovich
    Embedded Java: techniques and applications (tutorial abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:613- [Conf]
  17. Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, S. Prakash
    Efficient use of large don't cares in high-level and logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:272-278 [Conf]
  18. Reinaldo A. Bergamaschi, John Cohn
    The A to Z of SoCs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:790-798 [Conf]
  19. Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
    Be careful with don't cares. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:83-86 [Conf]
  20. Andreas Kuehlmann, Reinaldo A. Bergamaschi
    Timing analysis in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:349-354 [Conf]
  21. Salil Raje, Reinaldo A. Bergamaschi
    Generalized resource sharing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:326-332 [Conf]
  22. Pradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi
    Synthesis of Arrays and Records. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:614-619 [Conf]
  23. Andreas Kuehlmann, Reinaldo A. Bergamaschi
    High-Level State Machine Specification and Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:536-539 [Conf]
  24. C. Ross Ogilvie, Richard Ray, Robert Devins, Mark Kautzman, Michael Hale, Reinaldo A. Bergamaschi, Bob Lynch, Santosh Gaur
    Simplifying SoC design with the Customizable Control Processor Platform. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:402-403 [Conf]
  25. Daniel Gajski, Reinaldo A. Bergamaschi
    Panel Statement. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:8-9 [Conf]
  26. Reinaldo A. Bergamaschi
    Early and accurate analysis of SoCs: oxymoron or real? [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:3-6 [Conf]
  27. Reinaldo A. Bergamaschi, Salil Raje
    Observable Time Windows: Verifying High-Level Synthesis Results. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:2, pp:40-50 [Journal]
  28. Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau
    Automating the Design of SOCs Using Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:32-45 [Journal]
  29. John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin
    Early analysis tools for system-on-a-chip design. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:6, pp:691-708 [Journal]
  30. Martin Ohmacht, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Alan Gara, Mark Giampapa, Balaji Gopalsamy, Ruud A. Haring, Dirk Hoenicke, David J. Krolak, James A. Marcella, Ben J. Nathanson, Valentina Salapura, Michael E. Wazlowski
    Blue Gene/L compute chip: Memory and Ethernet subsystem. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2005, v:49, n:2-3, pp:255-264 [Journal]
  31. Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
    Don't cares in synthesis: theoretical pitfalls and practical solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:285-304 [Journal]
  32. Reinaldo A. Bergamaschi
    Bridging the domains of high-level and logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:582-596 [Journal]
  33. Reinaldo A. Bergamaschi
    SKOL: a system for logic synthesis and technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1342-1355 [Journal]
  34. Reinaldo A. Bergamaschi, Andreas Kuehlmann
    A system for production use of high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:233-243 [Journal]
  35. Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan
    Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:82-100 [Journal]

  36. Exploring power management in multi-core systems. [Citation Graph (, )][DBLP]

  37. Performance modeling for early analysis of multi-core systems. [Citation Graph (, )][DBLP]

  38. Redesign using state splitting. [Citation Graph (, )][DBLP]

  39. Challenges of the nanoscale era. [Citation Graph (, )][DBLP]

  40. Embedded Systems Week. [Citation Graph (, )][DBLP]

  41. The State of ESL Design [Roundtable]. [Citation Graph (, )][DBLP]

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