SCEAS

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Reinaldo A. Bergamaschi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

Reinaldo A. Bergamaschi, Grant Martin
System-level design tools: who needs them, who has them, and how much should they cost? [Citation Graph (0, 0)][DBLP]
CODES+ISSS, 2003, pp:79-80 [Conf]
Reinaldo A. Bergamaschi, Grant Martin, Wayne Wolf, Rolf Ernst, Kees A. Vissers, Jack Kouloheris
The future of system-level design: can we find the right solutions to the right problems at the right time? [Citation Graph (0, 0)][DBLP]
CODES+ISSS, 2003, pp:231- [Conf]
Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal
SEAS: a system for early analysis of SoCs. [Citation Graph (0, 0)][DBLP]
CODES+ISSS, 2003, pp:150-155 [Conf]
Francine Bacchini, Pierre G. Paulin, Reinaldo A. Bergamaschi, Raj Pawate, Arie Bernstein, Ramesh Chandra, Mohamed Ben-Romdhane
System level design: six success stories in search of an industry. [Citation Graph (0, 0)][DBLP]
DAC, 2004, pp:349-350 [Conf]
Reinaldo A. Bergamaschi
Productivity Issues in High-Level Design: Are Tools Solving the Real Problems? [Citation Graph (0, 0)][DBLP]
DAC, 1995, pp:674-677 [Conf]
Reinaldo A. Bergamaschi
Behavioral Network Graph: Unifying the Domains of High-Level and Logic Synthesis. [Citation Graph (0, 0)][DBLP]
DAC, 1999, pp:213-218 [Conf]
Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
Data-Path Synthesis Using Path Analysis. [Citation Graph (0, 0)][DBLP]
DAC, 1991, pp:591-596 [Conf]
Reinaldo A. Bergamaschi, Yunjian Jiang
State-based power analysis for systems-on-chip. [Citation Graph (0, 0)][DBLP]
DAC, 2003, pp:638-641 [Conf]
Reinaldo A. Bergamaschi, William R. Lee
Designing systems-on-chip using cores. [Citation Graph (0, 0)][DBLP]
DAC, 2000, pp:420-425 [Conf]
Reinaldo A. Bergamaschi, Donald Lobo, Andreas Kuehlmann
Control Optimization in High-Level Synthesis Using Behavioral Don't Cares. [Citation Graph (0, 0)][DBLP]
DAC, 1992, pp:657-661 [Conf]
Raul Compasano, Reinaldo A. Bergamaschi
Synthesis Using Path-Based scheduling: algorithms and Exercises. [Citation Graph (0, 0)][DBLP]
DAC, 1990, pp:450-455 [Conf]
Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi
Heterogeneous behavioral hierarchy for system level designs. [Citation Graph (0, 0)][DBLP]
DATE, 2006, pp:565-570 [Conf]
Wolfgang Rosenstiel, Reinaldo A. Bergamaschi, Frank Ghenassia, Thorsten Groetker, Masamichi Kawarabayashi, Marinus C. van Lier, Albrecht Mayer, Mike Meredith, Mark Milligan, Stuart Swan
Is there a Market for SystemC Tools? [Citation Graph (0, 0)][DBLP]
DATE, 2005, pp:950- [Conf]
Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi
Modeling and Integration of Peripheral Devices in Embedded Systems. [Citation Graph (0, 0)][DBLP]
DATE, 2003, pp:10136-10141 [Conf]
Reinaldo A. Bergamaschi
The Effects of False Paths in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
ICCAD, 1991, pp:80-83 [Conf]
Reinaldo A. Bergamaschi, Brian M. Barry, John Duimovich
Embedded Java: techniques and applications (tutorial abstract). [Citation Graph (0, 0)][DBLP]
ICCAD, 1999, pp:613- [Conf]
Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, S. Prakash
Efficient use of large don't cares in high-level and logic synthesis. [Citation Graph (0, 0)][DBLP]
ICCAD, 1995, pp:272-278 [Conf]
Reinaldo A. Bergamaschi, John Cohn
The A to Z of SoCs. [Citation Graph (0, 0)][DBLP]
ICCAD, 2002, pp:790-798 [Conf]
Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
Be careful with don't cares. [Citation Graph (0, 0)][DBLP]
ICCAD, 1995, pp:83-86 [Conf]
Andreas Kuehlmann, Reinaldo A. Bergamaschi
Timing analysis in high-level synthesis. [Citation Graph (0, 0)][DBLP]
ICCAD, 1992, pp:349-354 [Conf]
Salil Raje, Reinaldo A. Bergamaschi
Generalized resource sharing. [Citation Graph (0, 0)][DBLP]
ICCAD, 1997, pp:326-332 [Conf]
Pradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi
Synthesis of Arrays and Records. [Citation Graph (0, 0)][DBLP]
ICCD, 1999, pp:614-619 [Conf]
Andreas Kuehlmann, Reinaldo A. Bergamaschi
High-Level State Machine Specification and Synthesis. [Citation Graph (0, 0)][DBLP]
ICCD, 1992, pp:536-539 [Conf]
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark Kautzman, Michael Hale, Reinaldo A. Bergamaschi, Bob Lynch, Santosh Gaur
Simplifying SoC design with the Customizable Control Processor Platform. [Citation Graph (0, 0)][DBLP]
ICCD, 2003, pp:402-403 [Conf]
Daniel Gajski, Reinaldo A. Bergamaschi
Panel Statement. [Citation Graph (0, 0)][DBLP]
ISSS, 1999, pp:8-9 [Conf]
Reinaldo A. Bergamaschi
Early and accurate analysis of SoCs: oxymoron or real? [Citation Graph (0, 0)][DBLP]
SLIP, 2004, pp:3-6 [Conf]
Reinaldo A. Bergamaschi, Salil Raje
Observable Time Windows: Verifying High-Level Synthesis Results. [Citation Graph (0, 0)][DBLP]
IEEE Design & Test of Computers, 1997, v:14, n:2, pp:40-50 [Journal]
Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau
Automating the Design of SOCs Using Cores. [Citation Graph (0, 0)][DBLP]
IEEE Design & Test of Computers, 2001, v:18, n:5, pp:32-45 [Journal]
John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin
Early analysis tools for system-on-a-chip design. [Citation Graph (0, 0)][DBLP]
IBM Journal of Research and Development, 2002, v:46, n:6, pp:691-708 [Journal]
Martin Ohmacht, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Alan Gara, Mark Giampapa, Balaji Gopalsamy, Ruud A. Haring, Dirk Hoenicke, David J. Krolak, James A. Marcella, Ben J. Nathanson, Valentina Salapura, Michael E. Wazlowski
Blue Gene/L compute chip: Memory and Ethernet subsystem. [Citation Graph (0, 0)][DBLP]
IBM Journal of Research and Development, 2005, v:49, n:2-3, pp:255-264 [Journal]
Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
Don't cares in synthesis: theoretical pitfalls and practical solutions. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:285-304 [Journal]
Reinaldo A. Bergamaschi
Bridging the domains of high-level and logic synthesis. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:582-596 [Journal]
Reinaldo A. Bergamaschi
SKOL: a system for logic synthesis and technology mapping. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1342-1355 [Journal]
Reinaldo A. Bergamaschi, Andreas Kuehlmann
A system for production use of high-level synthesis. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:233-243 [Journal]
Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan
Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:82-100 [Journal]
Exploring power management in multi-core systems. [Citation Graph (, )][DBLP]
Performance modeling for early analysis of multi-core systems. [Citation Graph (, )][DBLP]
Redesign using state splitting. [Citation Graph (, )][DBLP]
Challenges of the nanoscale era. [Citation Graph (, )][DBLP]
Embedded Systems Week. [Citation Graph (, )][DBLP]
The State of ESL Design [Roundtable]. [Citation Graph (, )][DBLP]

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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP