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Subhrajit Bhattacharya: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal
    SEAS: a system for early analysis of SoCs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:150-155 [Conf]
  2. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Clock Period Optimization During Resource Sharing and Assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:195-200 [Conf]
  3. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:491-496 [Conf]
  4. Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
    Keeping hot chips cool. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:285-288 [Conf]
  5. Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama
    Verification of RTL generated from scheduled behavior in a high-level synthesis flow. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:517-524 [Conf]
  6. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Provably correct high-level timing analysis without path sensitization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:736-742 [Conf]
  7. Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya
    Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:458-466 [Conf]
  8. Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin
    A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:482-487 [Conf]
  9. Toshiharu Asaka, Masaaki Yoshida, Subhrajit Bhattacharya, Sujit Dey
    H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:265-274 [Conf]
  10. Subhrajit Bhattacharya, Sujit Dey
    H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:74-80 [Conf]
  11. Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau
    Automating the Design of SOCs Using Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:32-45 [Journal]
  12. John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin
    Early analysis tools for system-on-a-chip design. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:6, pp:691-708 [Journal]
  13. Martin Ohmacht, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Alan Gara, Mark Giampapa, Balaji Gopalsamy, Ruud A. Haring, Dirk Hoenicke, David J. Krolak, James A. Marcella, Ben J. Nathanson, Valentina Salapura, Michael E. Wazlowski
    Blue Gene/L compute chip: Memory and Ethernet subsystem. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2005, v:49, n:2-3, pp:255-264 [Journal]
  14. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Fast true delay estimation during high level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1088-1105 [Journal]
  15. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:285-307 [Journal]
  16. Subhrajit Bhattacharya, Franc Brglez, Sujit Dey
    Transformations and resynthesis for testability of RT-level control-data path specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:304-318 [Journal]

  17. Search-Based Path Planning with Homotopy Class Constraints. [Citation Graph (, )][DBLP]

  18. An RTL methodology to enable low overhead combinational testing. [Citation Graph (, )][DBLP]

  19. Search-based planning for a legged robot over rough terrain. [Citation Graph (, )][DBLP]

  20. Multi-agent path planning with multiple tasks and distance constraints. [Citation Graph (, )][DBLP]

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