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Yong Dou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong
    Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:567-573 [Conf]
  2. YuXing Tang, Kun Deng, Xiaodong Wang, Yong Dou, Xingming Zhou
    RIMP: Runtime Implicit Predication. [Citation Graph (0, 0)][DBLP]
    APPT, 2005, pp:71-80 [Conf]
  3. Yong Dou, Xicheng Lu
    LEAP: A Data Driven Loop Engine on Array Processor. [Citation Graph (0, 0)][DBLP]
    APPT, 2003, pp:12-22 [Conf]
  4. Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G. N. Gaydadjiev
    64-bit floating-point FPGA matrix multiplication. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:86-95 [Conf]
  5. Song Lu, BaoHua Fan, Yong Dou, Xiaodong Yang
    Clustering Multicast on Hypercube Network. [Citation Graph (0, 0)][DBLP]
    HPCC, 2006, pp:61-70 [Conf]
  6. Xue-Jun Yang, Yong Dou, Qing-Feng Hu
    Progress and Challenges in High Performance Computer Technology. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:5, pp:674-681 [Journal]
  7. Yong Dou, Jinbo Xu
    FPGA-Accelerated Active Shape Model for Real-Time People Tracking. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:268-279 [Conf]
  8. Fei Xia, Yong Dou
    Reducing Storage Requirements in Accelerating Algorithm of Global BioSequence Alignment on FPGA. [Citation Graph (0, 0)][DBLP]
    APPT, 2007, pp:90-99 [Conf]
  9. Bao-Feng Li, Yong Dou
    FIDP: A Novel Architecture for Lifting-Based 2D DWT in JPEG2000. [Citation Graph (0, 0)][DBLP]
    MMM (2), 2007, pp:373-382 [Conf]
  10. Xiaodong Yang, Shengmei Mou, Yong Dou
    FPGA-Accelerated Molecular Dynamics Simulations: An Overview. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:293-301 [Conf]
  11. Yazhuo Dong, Yong Dou, Jie Zhou
    Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:110-121 [Conf]
  12. Yong Dou, Jinhui Xu, Guiming Wu
    The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:155-166 [Conf]

  13. Implementation of Rotation Invariant Multi-View Face Detection on FPGA. [Citation Graph (, )][DBLP]


  14. A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA. [Citation Graph (, )][DBLP]


  15. FPGA SAR Processor with Window Memory Accesses. [Citation Graph (, )][DBLP]


  16. Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization. [Citation Graph (, )][DBLP]


  17. A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications. [Citation Graph (, )][DBLP]


  18. Fine-Grained Parallel Zuker Algorithm Accelerator with Storage Optimization on FPGA. [Citation Graph (, )][DBLP]


  19. Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA. [Citation Graph (, )][DBLP]


  20. Distributed Collaborative Partition Method of Reconfigurable SoC Using Ant Colony Optimization. [Citation Graph (, )][DBLP]


  21. FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications. [Citation Graph (, )][DBLP]


  22. A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs. [Citation Graph (, )][DBLP]


  23. FPGA accelerating three QR decomposition algorithms in the unified pipelined framework. [Citation Graph (, )][DBLP]


  24. Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. [Citation Graph (, )][DBLP]


  25. Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA. [Citation Graph (, )][DBLP]


  26. Exploiting Fine-Grained Pipeline Parallelism for Wavefront Computations on Multicore Platforms. [Citation Graph (, )][DBLP]


  27. FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing. [Citation Graph (, )][DBLP]


  28. DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor. [Citation Graph (, )][DBLP]


  29. FPGA-based Memory-efficient Parallel RNA Secondary Structure Prediction Accelerator Using SCFGs. [Citation Graph (, )][DBLP]


  30. Rectangularly Multi-Module Memory System with Table-Based Dynamic Addressing Scheme. [Citation Graph (, )][DBLP]


  31. Families of FPGA-Based Accelerators for BLAST Algorithm with Multi-seeds Detection and Parallel Extension. [Citation Graph (, )][DBLP]


  32. Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension. [Citation Graph (, )][DBLP]


  33. Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. [Citation Graph (, )][DBLP]


  34. Fine-grained parallel RNAalifold algorithm for RNA secondary structure prediction on FPGA. [Citation Graph (, )][DBLP]


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