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Vittorio Zaccaria: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    A design framework to efficiently explore energy-delay tradeoffs. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:260-265 [Conf]
  2. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Instruction-level power estimation for embedded VLIW cores. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:34-38 [Conf]
  3. Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon
    Energy estimation and optimization of embedded VLIW processors based on instruction clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:886-891 [Conf]
  4. Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon
    An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1128- [Conf]
  5. Andrea Bona, Vittorio Zaccaria, Roberto Zafalon
    System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:318-323 [Conf]
  6. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
    Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20182-20187 [Conf]
  7. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Exploiting data forwarding to reduce the power budget of VLIW embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:252-257 [Conf]
  8. Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:440-443 [Conf]
  9. Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Branch prediction techniques for low-power VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:225-228 [Conf]
  10. Gianluca Palermo, Cristina Silvano, S. Valsecchi, Vittorio Zaccaria
    A system-level methodology for fast multi-objective design space exploration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:92-95 [Conf]
  11. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Power Exploration for Embedded VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:498-503 [Conf]
  12. Guido Bertoni, A. Bircan, Luca Breveglieri, Pasqualina Fragneto, Marco Macchetti, Vittorio Zaccaria
    About the performances of the Advanced Encryption Standard in embedded systems with cache memory. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:145-148 [Conf]
  13. William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Fast system-level exploration of memory architectures driven by energy-delay metrics. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:502-505 [Conf]
  14. Guido Bertoni, Vittorio Zaccaria, Luca Breveglieri, Matteo Monchiero, Gianluca Palermo
    AES Power Attack Based on Induced Cache Miss and Countermeasure. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:586-591 [Conf]
  15. William Fornaciari, Vincenzo Piuri, Andrea Prestileo, Vittorio Zaccaria
    An Agent-Based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems. [Citation Graph (0, 0)][DBLP]
    MATA, 2001, pp:153-162 [Conf]
  16. Andrea Bona, Vittorio Zaccaria, Roberto Zafalon
    Low Effort, High Accuracy Network-on-Chip Power Macro Modeling. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:541-552 [Conf]
  17. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
    A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:249-258 [Conf]
  18. Lorenzo Salvemini, Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:672-678 [Conf]
  19. Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:515-524 [Journal]
  20. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    An instruction-level energy model for embedded VLIW architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:998-1010 [Journal]
  21. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Low-power data forwarding for VLIW embedded architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:614-622 [Journal]

  22. Variability-aware robust design space exploration of chip multiprocessor architectures. [Citation Graph (, )][DBLP]


  23. A correlation-based design space exploration methodology for multi-processor systems-on-chip. [Citation Graph (, )][DBLP]


  24. An industrial design space exploration framework for supporting run-time resource management on multi-core systems. [Citation Graph (, )][DBLP]


  25. Energy-performance design space exploration in SMT architectures exploiting selective load value predictions. [Citation Graph (, )][DBLP]


  26. Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration. [Citation Graph (, )][DBLP]


  27. Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip. [Citation Graph (, )][DBLP]


  28. Robust optimization of SoC architectures: A multi-scenario approach. [Citation Graph (, )][DBLP]


  29. An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods. [Citation Graph (, )][DBLP]


  30. Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques. [Citation Graph (, )][DBLP]


  31. An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints. [Citation Graph (, )][DBLP]


  32. A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip. [Citation Graph (, )][DBLP]


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