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Frédéric Rousseau :
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Laurent Freund , Denis Dupont , Michel Israël , Frédéric Rousseau Interface Optimization During Hardware-Software Partitioning. [Citation Graph (0, 0)][DBLP ] CODES, 1997, pp:75-80 [Conf ] Adriano Sarmento , Lobna Kriaa , Arnaud Grasset , Mohamed-Wassim Youssef , Aimen Bouchhima , Frédéric Rousseau , Wander O. Cesário , Ahmed Amine Jerraya Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2005, pp:261-266 [Conf ] Frédéric Rousseau , J. M. Bergé , Michel Israël Hardware/Software Partitioning for Telecommunications Systems. [Citation Graph (0, 0)][DBLP ] COMPSAC, 1996, pp:483-0 [Conf ] Ferid Gharsalli , Samy Meftali , Frédéric Rousseau , Ahmed Amine Jerraya Automatic generation of embedded memory wrapper for multiprocessor SoC. [Citation Graph (0, 0)][DBLP ] DAC, 2002, pp:596-601 [Conf ] Samy Meftali , Ferid Gharsalli , Frédéric Rousseau , Ahmed Amine Jerraya Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2001, pp:193-204 [Conf ] Ahmed Amine Jerraya , Damien Lyonnard , Samy Meftali , Frédéric Rousseau , Ferid Gharsalli Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design. [Citation Graph (0, 0)][DBLP ] ISSS, 2002, pp:26-31 [Conf ] Laurent Freund , Michel Israël , Frédéric Rousseau , J. M. Bergé , Michel Auguin , Cécile Belleudy , Guy Gogniat A Codesign Experiment in Acoustic Echo Cancellation: GMDFa. [Citation Graph (0, 0)][DBLP ] ISSS, 1996, pp:83-0 [Conf ] Samy Meftali , Ferid Gharsalli , Frédéric Rousseau , Ahmed Amine Jerraya An optimal memory allocation for application-specific multiprocessor system-on-chip. [Citation Graph (0, 0)][DBLP ] ISSS, 2001, pp:19-24 [Conf ] Arnaud Grasset , Frédéric Rousseau , Ahmed Amine Jerraya Network Interface Generation for MPSOC: From Communication Service Requirements to RTL Implementation. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2004, pp:66-69 [Conf ] Arnaud Grasset , Frédéric Rousseau , Ahmed Amine Jerraya Automatic Generation of Component Wrappers by Composition of Hardware Library Elements Starting from Communication Service Specification. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2005, pp:47-53 [Conf ] Arif Sasongko , Amer Baghdadi , Frédéric Rousseau , Ahmed Amine Jerraya Embedded Application Prototyping on a Communication-Restricted Reconfigurable. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2003, pp:33-39 [Conf ] Benaoumeur Senouci , Aimen Bouchhima , Frédéric Rousseau , Frédéric Pétrot , Ahmed Amine Jerraya Fast Prototyping of POSIX Based Applications on a Multiprocessor SoC Architecture: "Hardware-Dependent Software Oriented Approach". [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2006, pp:69-75 [Conf ] Michel Metzger , Frederic Bastien , F. Rousseau , Julie Vachon , El Mostapha Aboulhamid Introspection Mechanisms for Semi-Formal Verification in a System-Level Design Environment. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2006, pp:91-97 [Conf ] Laurent Freund , Michel Israël , Frédéric Rousseau , J. M. Bergé , Michel Auguin , Cécile Belleudy , Guy Gogniat A codesign experiment in acoustic echo cancellation GMDF. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:4, pp:365-383 [Journal ] Ferid Gharsalli , Frédéric Rousseau , Ahmed Amine Jerraya Conception des interfaces logiciel-matériel pour l'intégration des mémoires globales dans les systèmes monopuces. [Citation Graph (0, 0)][DBLP ] Technique et Science Informatiques, 2005, v:24, n:4, pp:369-394 [Journal ] Xavier Guerin , Katalin Popovici , Wassim Youssef , Frédéric Rousseau , Ahmed Amine Jerraya Flexible Application Software Generation for Heterogeneous Multi-Processor System-on-Chip. [Citation Graph (0, 0)][DBLP ] COMPSAC (1), 2007, pp:279-286 [Conf ] Katalin Popovici , Xavier Guerin , Frédéric Rousseau , Pier Stanislao Paolucci , Ahmed Amine Jerraya Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2007, pp:113-122 [Conf ] Alena Tsikhanovich , F. Rousseau , El Mostapha Aboulhamid , Guy Bois Transaction Level Modeling in Hardware/Software System Design using .Net Framework. [Citation Graph (0, 0)][DBLP ] CCECE, 2006, pp:140-143 [Conf ] Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation. [Citation Graph (, )][DBLP ] Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor Prototyping: New Challenges for Embedded Software Designers. [Citation Graph (, )][DBLP ] Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips. [Citation Graph (, )][DBLP ] Towards an Efficient Simulation of Multi-Language Descriptions of Heterogeneous Systems. [Citation Graph (, )][DBLP ] A Verification Tool Implementation using Introspection Mechanism. [Citation Graph (, )][DBLP ] Prototyping Multiprocessor System-on-Chip Applications: A Platform-Based Approach. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.305secs