The SCEAS System
Navigation Menu

Search the dblp DataBase


Carlos Carreras: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Carlos Carreras, J. C. López, María Luisa López, Luis Sánchez, Carlos Delgado Kloos, Natividad Martinez
    A Co-Design Methodology Based on Formal Specification and High-level Estimation. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:28-35 [Conf]
  2. Gerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
    A Generator of High-Speed Floating-Point Modules. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:306-307 [Conf]
  3. Juan A. López, Carlos Carreras, Gabriel Caffarena, Octavio Nieto-Taladriz
    Fast characterization of the noise bounds derived from coefficient and signal quantization. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:309-312 [Conf]
  4. Carlos Carreras, Juan A. López, Octavio Nieto-Taladriz
    Bit-Width Selection for Data-Path Implementations. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:114-121 [Conf]
  5. Carlos Carreras, Carlos A. López, Manuel V. Hermenegildo
    Analytic Model of a Cache Only Memory Architecture. [Citation Graph (0, 0)][DBLP]
    PARLE, 1994, pp:336-350 [Conf]
  6. Carlos Carreras, Manuel V. Hermenegildo
    Grid-Based Histogram Arithmetic for the Probabilistic Analysis of Functions. [Citation Graph (0, 0)][DBLP]
    SARA, 2000, pp:107-123 [Conf]
  7. Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
    High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  8. Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena
    Switching Activity Models for Power Estimation in FPGA Multipliers. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:201-213 [Conf]

  9. A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention. [Citation Graph (, )][DBLP]

  10. Analytical High-Level Power Model for LUT-Based Components. [Citation Graph (, )][DBLP]

  11. Floorplan-based FPGA interconnect power estimation in DSP circuits. [Citation Graph (, )][DBLP]

  12. A Practical Method for Testing High-Speed Networking Hardware Architectures. [Citation Graph (, )][DBLP]

  13. Adding Value to TCP/IP Based Information exchange Security by Specialized Hardware. [Citation Graph (, )][DBLP]

  14. Optimized Architectural Synthesis of Fixed-Point Datapaths. [Citation Graph (, )][DBLP]

  15. A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. [Citation Graph (, )][DBLP]

Search in 0.002secs, Finished in 0.003secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002