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Publications of Author

1. Andreas Hansson, Kees Goossens, Andrei Radulescu
   A unified approach to constrained mapping and routing on network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2005, pp:75-80 [Conf]
   
2. Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten
   A Monitoring-Aware Network-on-Chip Design Flow. [Citation Graph (0, 0)][DBLP]
   DSD, 2006, pp:97-106 [Conf]
   
3. Andreas Hansson, Martijn Coenen, Kees Goossens
   Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:954-959 [Conf]
   
4. Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal
   Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:117-122 [Conf]
   
5. Andreas Hansson, Kees Goossens
   Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases. [Citation Graph (0, 0)][DBLP]
   NOCS, 2007, pp:233-242 [Conf]
   
6. 
   Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. [Citation Graph (, )][DBLP]
   
   
7. 
   An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. [Citation Graph (, )][DBLP]
   
   
8. 
   The aethereal network on chip after ten years: goals, evolution, lessons, and future. [Citation Graph (, )][DBLP]
   
   
9. 
   Aelite: A flit-synchronous Network on Chip with composable and predictable services. [Citation Graph (, )][DBLP]
   
   
10. 
    Composable Resource Sharing Based on Latency-Rate Servers. [Citation Graph (, )][DBLP]
    
    
11. 
    Using Segmentation to Control the Retrieval of Data. [Citation Graph (, )][DBLP]
    
    
12. 
    Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. [Citation Graph (, )][DBLP]