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Shinya Honda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada
    RTOS-centric hardware/software cosimulator for embedded system design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:158-163 [Conf]
  2. Shinya Honda, Hiroaki Takada
    Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20138-20143 [Conf]
  3. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
    Function Call Optimization in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:522-529 [Conf]
  4. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
    Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:365-370 [Conf]
  5. Hiroaki Takada, Shinya Honda, Reiji Nishiyama, Hiroshi Yuyama
    Hardware/Software Co-Configuration for Multiprocessor SoPC. [Citation Graph (0, 0)][DBLP]
    WSTFEUS, 2003, pp:7-8 [Conf]
  6. Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
    A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:283-294 [Conf]
  7. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
    Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:261-270 [Conf]

  8. RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. [Citation Graph (, )][DBLP]

  9. Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis. [Citation Graph (, )][DBLP]

  10. CHStone: A benchmark program suite for practical C-based high-level synthesis. [Citation Graph (, )][DBLP]

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