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Hiroaki Takada: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada
    RTOS-centric hardware/software cosimulator for embedded system design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:158-163 [Conf]
  2. Shinya Honda, Hiroaki Takada
    Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20138-20143 [Conf]
  3. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
    Function Call Optimization in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:522-529 [Conf]
  4. Shan Ding, Naohiko Murakami, Hiroyuki Tomiyama, Hiroaki Takada
    A GA-based scheduling method for FlexRay systems. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:110-113 [Conf]
  5. Hiroyuki Tomiyama, Hiroaki Takada, Nikil D. Dutt
    Data Organization Exploration for Low-Energy Address Buses. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:128-133 [Conf]
  6. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
    Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:365-370 [Conf]
  7. Hiroaki Takada
    Introduction to the TOPPERS Project - Open Source RTOS for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISORC, 2003, pp:44-45 [Conf]
  8. Cai-Dong Wang, Hiroaki Takada, Ken Sakamura
    Priority Inheritance Spin Locks for Multiprocessor Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1996, pp:70-76 [Conf]
  9. Takayuki Wakabayashi, Hiroaki Takada
    Standardization approach of ITRON debugging interface specification and evaluation of its adaptability. [Citation Graph (0, 0)][DBLP]
    LCTES-SCOPES, 2002, pp:65-74 [Conf]
  10. Hiroshi Miyamoto, Shinichi Iiyama, Hiroyuki Tomiyama, Hiroaki Takada, Hiroshi Nakashima
    An Efficient Search Algorithm of Worst-Case Cache Flush Timings. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:45-52 [Conf]
  11. Hiroaki Takada, Ken Sakamura
    Real-time scalability of nested spin locks. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1995, pp:160-167 [Conf]
  12. Hiroaki Takada, Ken Sakamura
    Schedulability of generalized multiframe task sets under static priority assignment. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1997, pp:80-86 [Conf]
  13. Hiroaki Takada, Shinya Honda, Reiji Nishiyama, Hiroshi Yuyama
    Hardware/Software Co-Configuration for Multiprocessor SoPC. [Citation Graph (0, 0)][DBLP]
    WSTFEUS, 2003, pp:7-8 [Conf]
  14. Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
    A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:283-294 [Conf]
  15. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
    Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:261-270 [Conf]
  16. Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada
    Scheduling Algorithms for I/O Blockings with a Multi-frame Task Model. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:386-393 [Conf]
  17. Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada
    Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:241-254 [Conf]

  18. A Visual Modeling Environment for Embedded Component Systems. [Citation Graph (, )][DBLP]


  19. Analyzing and optimizing energy efficiency of algorithms on DVS systems a first step towards algorithmic energy minimization. [Citation Graph (, )][DBLP]


  20. RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. [Citation Graph (, )][DBLP]


  21. Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems. [Citation Graph (, )][DBLP]


  22. Improved Policies for Drowsy Caches in Embedded Processors. [Citation Graph (, )][DBLP]


  23. Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis. [Citation Graph (, )][DBLP]


  24. A Software Framework for Energy and Performance Tradeoff in Fixed-Priority Hard Real-Time Embedded Systems. [Citation Graph (, )][DBLP]


  25. A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. [Citation Graph (, )][DBLP]


  26. SSEST: Summer school on embedded system technologies. [Citation Graph (, )][DBLP]


  27. CHStone: A benchmark program suite for practical C-based high-level synthesis. [Citation Graph (, )][DBLP]


  28. A New Specification of Software Components for Embedded Systems. [Citation Graph (, )][DBLP]


  29. Practical Energy-Aware Scheduling for Real-Time Multiprocessor Systems. [Citation Graph (, )][DBLP]


  30. Optimization of Component Connections for an Embedded Component System. [Citation Graph (, )][DBLP]


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