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Kamal S. Khouri: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
    Analytical models for leakage power estimation of memory array structures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:146-151 [Conf]
  2. Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
    Floorplan driven leakage power aware IP-based SoC design space exploration. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:118-123 [Conf]
  3. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-Case Computation: A High-Level Technique for Power and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:56-61 [Conf]
  4. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:848-854 [Conf]
  5. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Memory binding for performance optimization of control-flow intensive behaviors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:482-488 [Conf]
  6. Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
    Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:244-250 [Conf]
  7. Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
    IDAP: A Tool for High Level Power Estimation of Custom Array Structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:113-119 [Conf]
  8. Kamal S. Khouri, Niraj K. Jha
    Leakage Power Analysis and Reduction during Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:561-564 [Conf]
  9. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Fast high-level power estimation for control-flow intensive design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:299-304 [Conf]
  10. Kamal S. Khouri, Niraj K. Jha
    Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:523-529 [Conf]
  11. Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri
    A Methodology for Accurate Modeling of Energy Dissipation in Array Structures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:320-0 [Conf]
  12. Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
    STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:559-564 [Conf]
  13. Kamal S. Khouri, Niraj K. Jha
    Clock selection for performance optimization of control-flowintensive behaviors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:158-165 [Journal]
  14. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    High-level synthesis of low-power control-flow intensive circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1715-1729 [Journal]
  15. Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
    Wavesched: a novel scheduling technique for control-flow intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:505-523 [Journal]
  16. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-case computation: a high-level energy and performance optimization technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:33-49 [Journal]
  17. Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
    IDAP: a tool for high-level power estimation of custom array structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1361-1369 [Journal]
  18. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Memory binding for performance optimization of control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:513-524 [Journal]
  19. Kamal S. Khouri, Niraj K. Jha
    Leakage power analysis and reduction during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:876-885 [Journal]

  20. LEAF: A System Level Leakage-Aware Floorplanner for SoCs. [Citation Graph (, )][DBLP]


  21. TRAM: A tool for Temperature and Reliability Aware Memory Design. [Citation Graph (, )][DBLP]


  22. Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. [Citation Graph (, )][DBLP]


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