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Marek Jersak :
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Marek Jersak , Kai Richter , Rafik Henia , Rolf Ernst , Frank Slomka Transformation of SDL specifications for system-level timing analysis. [Citation Graph (0, 0)][DBLP ] CODES, 2002, pp:121-126 [Conf ] Marek Jersak , Rolf Ernst Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:454-459 [Conf ] Kai Richter , Dirk Ziegenbein , Marek Jersak , Rolf Ernst Model composition for scheduling analysis in platform design. [Citation Graph (0, 0)][DBLP ] DAC, 2002, pp:287-292 [Conf ] Marek Jersak , Rafik Henia , Rolf Ernst Context-Aware Performance Analysis for Efficient Embedded System Design. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:1046-1051 [Conf ] Marek Jersak , Kai Richter , Rolf Ernst , Jörn-Christian Braam , Zheng-Yu Jiang , Fabian Wolf Formal Methods for Integration of Automotive Software. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:20045-20050 [Conf ] Christian Haubelt , Marek Jersak , Kai Richter , Karsten Strehl , Dirk Ziegenbein , Rolf Ernst , Jürgen Teich , Lothar Thiele SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung (2), 2005, pp:693-697 [Conf ] Kai Richter , Dirk Ziegenbein , Marek Jersak , Rolf Ernst Bottom-Up Performance Analysis of HW/SW Platforms. [Citation Graph (0, 0)][DBLP ] DIPES, 2002, pp:173-183 [Conf ] Marek Jersak , Ying Cai , Dirk Ziegenbein , Rolf Ernst A Transformational Approach to Constraint Relaxation of a Time-driven Simulation Model. [Citation Graph (0, 0)][DBLP ] ISSS, 2000, pp:137-142 [Conf ] Dirk Ziegenbein , Fabian Wolf , Kai Richter , Marek Jersak , Rolf Ernst Interval-Based Analysis of Software Processes. [Citation Graph (0, 0)][DBLP ] LCTES/OM, 2001, pp:94-101 [Conf ] Razvan Racu , Marek Jersak , Rolf Ernst Applying Sensitivity Analysis in Real-Time Distributed Systems. [Citation Graph (0, 0)][DBLP ] IEEE Real-Time and Embedded Technology and Applications Symposium, 2005, pp:160-169 [Conf ] Arne Hamann , Marek Jersak , Kai Richter , Rolf Ernst Design Space Exploration and System Optimization with SymTA/S-- Symbolic Timing Analysis for Systems. [Citation Graph (0, 0)][DBLP ] RTSS, 2004, pp:469-478 [Conf ] Kai Richter , Marek Jersak , Rolf Ernst A Formal Approach to MpSoC Performance Verification. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 2003, v:36, n:4, pp:60-67 [Journal ] Arne Hamann , Marek Jersak , Kai Richter , Rolf Ernst A framework for modular analysis and exploration of heterogeneous embedded systems. [Citation Graph (0, 0)][DBLP ] Real-Time Systems, 2006, v:33, n:1-3, pp:101-137 [Journal ] Marek Jersak , Kai Richter , Rolf Ernst Interval-based analysis in embedded system design. [Citation Graph (0, 0)][DBLP ] Mathematics and Computers in Simulation, 2004, v:66, n:2-3, pp:231-242 [Journal ] Automotive networks: are new busses and gateways the answer or just another challenge? [Citation Graph (, )][DBLP ] Formal Methods in System and MpSoC Performance Analysis and Optimisation. [Citation Graph (, )][DBLP ] Learning early-stage platform dimensioning from late-stage timing verification. [Citation Graph (, )][DBLP ] ALL-TIMES - A European Project on Integrating Timing Technology. [Citation Graph (, )][DBLP ] Timing Validation of Automotive Software. [Citation Graph (, )][DBLP ] Early Architecture Exploration with SymTA/S. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.003secs