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Alex Doboli: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sankalp Kallakuri, Alex Doboli
    Energy conscious online architecture adaptation for varying latency constraints in sensor network applications. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:148-153 [Conf]
  2. Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri
    Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:951-957 [Conf]
  3. Alex Doboli, Ranga Vemuri
    Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:629-634 [Conf]
  4. Ying Wei, Alex Doboli
    Systematic development of analog circuit structural macromodels through behavioral model decoupling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:57-62 [Conf]
  5. Ying Wei, Alex Doboli
    Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1023-1028 [Conf]
  6. Alex Doboli
    Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:612-619 [Conf]
  7. Simona Doboli, Gaurav Gothoskar, Alex Doboli
    Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11098-11099 [Conf]
  8. Alex Doboli, Ranga Vemuri
    A regularity-based hierarchical symbolic analysis method for large-scale analog networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:806- [Conf]
  9. Alex Doboli, Ranga Vemuri
    A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:760-769 [Conf]
  10. Alex Doboli, Ranga Vemuri
    A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:338-345 [Conf]
  11. Sankalp Kallakuri, Alex Doboli, Eugene A. Feinberg
    Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:826-827 [Conf]
  12. Hua Tang, Ying Wei, Alex Doboli
    MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:264-269 [Conf]
  13. Nattawut Thepayasuwan, Alex Doboli
    Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:108-113 [Conf]
  14. Ying Wei, Hua Tang, Alex Doboli
    Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:393-398 [Conf]
  15. Hui Zhang, Yang Zhao, Alex Doboli
    ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:156-161 [Conf]
  16. Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Eugene A. Feinberg
    A continuous time markov decision process based on-chip buffer allocation methodology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:345-348 [Conf]
  17. Hua Tang, Hui Zhang, Alex Doboli
    Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:207-210 [Conf]
  18. Yulei Weng, Alex Doboli
    Digital cell macro-model with regular substrate template and EKV based MOSFET model. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:172-175 [Conf]
  19. Nattawut Thepayasuwan, Vaishali Damle, Alex Doboli
    Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:126-133 [Conf]
  20. Nattawut Thepayasuwan, Alex Doboli
    Hardware-Software Co-Design of Resource Constrained Systems on a Chip. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshops, 2004, pp:818-823 [Conf]
  21. Alex Doboli, Ranga Vemuri
    A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:305-317 [Conf]
  22. Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Simona Doboli
    Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1044-1047 [Conf]
  23. Hua Tang, Alex Doboli
    Parameter domain pruning for improving convergence of synthesis algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1282-1285 [Conf]
  24. Nattawut Thepayasuwan, Hua Tang, Alex Doboli
    An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:629-632 [Conf]
  25. Hui Zhang, Alex Doboli
    Fast time-domain symbolic simulation for synthesis of sigma-delta analog-digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:125-128 [Conf]
  26. Hui Zhang, Preethi Karthik, Hua Tang, Alex Doboli
    An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5629-5632 [Conf]
  27. Alex Doboli, Ranga Vemuri
    Hierarchical performance optimization for synthesis of linear analog systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:431-434 [Conf]
  28. Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex Doboli
    Hardware/Software Partitioning with Iterative Improvement Heuristics. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:71-76 [Conf]
  29. Sankalp Kallakuri, Alex Doboli, Simona Doboli
    Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration Policies. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:199-206 [Conf]
  30. Hua Tang, Hui Zhang, Alex Doboli
    Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:266-271 [Conf]
  31. Nattawut Thepayasuwan, Alex Doboli
    OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:264-265 [Conf]
  32. Nattawut Thepayasuwan, Alex Doboli
    A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:57-60 [Conf]
  33. Hua Tang, Alex Doboli
    Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:41-44 [Conf]
  34. Yulei Weng, Alex Doboli
    Smart Sensor Architecture Customized for Image Processing Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time and Embedded Technology and Applications Symposium, 2004, pp:396-403 [Conf]
  35. Sankalp Kallakuri, Alex Doboli, Simona Doboli
    Applying Stochastic Modeling to Bus Arbitration for Network-On-Chip Systems. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:261-265 [Conf]
  36. Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri
    Hierarchical constraint transformation based on genetic optimization for analog system synthesis. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:3, pp:267-290 [Journal]
  37. Sankalp Kallakuri, Alex Doboli, Simona Doboli
    Applying stochastic modeling to bus arbitration for systems-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:183-191 [Journal]
  38. Alex Doboli, Ranga Vemuri
    Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1504-1520 [Journal]
  39. Alex Doboli, Ranga Vemuri
    Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1556-1568 [Journal]
  40. Hua Tang, Alex Doboli
    High-level synthesis of /spl Delta//spl Sigma/ Modulator topologies optimized for complexity, sensitivity, and power consumption. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:597-607 [Journal]
  41. Hua Tang, Hui Zhang, Alex Doboli
    Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1421-1440 [Journal]
  42. Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:238-271 [Journal]
  43. Nattawut Thepayasuwan, Alex Doboli
    Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:525-538 [Journal]
  44. Pengbo Sun, Ying Wei, Alex Doboli
    Flexibility-oriented design methodology for reconfigurable DeltaSigma modulators. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:415-420 [Conf]
  45. Ying Wei, Alex Doboli
    Library of structural analog cell macromodels for design of continuous-time reconfigurable Delta Sigma modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  46. Meng Wang, Alex Doboli, Thomas G. Robertazzi, Simona Doboli, Daniel Curiac
    Towards Scalable Distributed Control of Unmanned Autonomous Vehicles. [Citation Graph (0, 0)][DBLP]
    SACI, 2007, pp:147-152 [Conf]
  47. Sankalp S. Kallakuri, Alex Doboli, Eugene A. Feinberg
    Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  48. Hui Zhang, Simona Doboli, Hua Tang, Alex Doboli
    Compiled code simulation of analog and mixed-signal systems using piecewise linear modeling of nonlinear parameters: A case study for DeltaSigma modulator simulation. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:193-208 [Journal]
  49. Sankalp S. Kallakuri, Alex Doboli
    Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:240-245 [Journal]
  50. Petru Eles, Alex Doboli, Paul Pop, Zebo Peng
    Scheduling with bus access optimization for distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:472-491 [Journal]

  51. Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes. [Citation Graph (, )][DBLP]


  52. Linear programming approach for performance-driven data aggregation in networks of embedded sensors. [Citation Graph (, )][DBLP]


  53. PNet: A Grid Type Sensor Network of Reconfigurable Nodes. [Citation Graph (, )][DBLP]


  54. SoC Design Point Selection for Dynamic Adaptation under Continuously Varying Throughput Constraints. [Citation Graph (, )][DBLP]


  55. Corrections of sensing error in video-based traffic surveillance. [Citation Graph (, )][DBLP]


  56. SystemC Simulation of Continuous-Time $Sigma-Delta$ Analog-Digital Converters in the Presence of Non-linearities. [Citation Graph (, )][DBLP]


  57. Towards High-Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS Specifications. [Citation Graph (, )][DBLP]


  58. Knowledge based System for Reliable Perimeter Protection using Sensor Networks. [Citation Graph (, )][DBLP]


  59. Self-destruction Procedure for Cluster-tree Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  60. Towards a Specification Notation for High-Level Synthesis of Mixed-Signal and Analog Systems. [Citation Graph (, )][DBLP]


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