Search the dblp DataBase

Publications of Author

1. Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild
   FlexPath NP: a network processor concept with application-driven flexible processing paths. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2005, pp:279-284 [Conf]
   
2. Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
   Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:248-253 [Conf]
   
3. Winthir Brunnbauer, Thomas Wild, Jürgen Foag, Nuria Pazos
   A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. [Citation Graph (0, 0)][DBLP]
   DSD, 2003, pp:98-103 [Conf]
   
4. Jürgen Foag, Nuria Pazos, Thomas Wild, Winthir Brunnbauer
   Self-Adaptive Parallel Processing Architecture For High-speed Networking. [Citation Graph (0, 0)][DBLP]
   HPCS, 2002, pp:45-52 [Conf]
   
5. Jürgen Foag, Thomas Wild
   Queuing Algorithm for Speculative Network Processors. [Citation Graph (0, 0)][DBLP]
   HPCS, 2004, pp:3-8 [Conf]
   
6. Jürgen Foag, Thomas Wild, Nuria Pazos, Winthir Brunnbauer
   Predictive methodology for high-performance networking. [Citation Graph (0, 0)][DBLP]
   ISCC, 2002, pp:169-174 [Conf]
   
7. Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf
   A Programmable Stream Processing Engine for Packet Manipulation in Network Processors. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2007, pp:259-264 [Conf]
   
8. Thomas Wild, Jürgen Foag, Nuria Pazos, Winthir Brunnbauer
   Mapping and Scheduling for Architecture Exploration of Networking SoCs. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:376-381 [Conf]
   
9. Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf
   Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. [Citation Graph (0, 0)][DBLP]
   ICSAMOS, 2006, pp:152-159 [Conf]
   
10. Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf
    Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:703-718 [Journal]
    
11. 
    A Hardware Packet Re-Sequencer Unit for Network Processors. [Citation Graph (, )][DBLP]
    
    
12. 
    System Level Simulation of Autonomic SoCs with TAPES. [Citation Graph (, )][DBLP]
    
    
13. 
    Buffer allocation for advanced packet segmentation in Network Processors. [Citation Graph (, )][DBLP]
    
    
14. 
    Reconfigurable Processing Units vs. Reconfigurable Interconnects. [Citation Graph (, )][DBLP]
    
    
15. 
    Power Estimation of Time Variant SoCs with TAPES. [Citation Graph (, )][DBLP]
    
    
16. 
    Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources. [Citation Graph (, )][DBLP]
    
    
17. 
    Network processors. [Citation Graph (, )][DBLP]
    
    
18. 
    An Application-Aware Load Balancing Strategy for Network Processors. [Citation Graph (, )][DBLP]
    
    
19. 
    Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design. [Citation Graph (, )][DBLP]
    
    
20. 
    Improving memory subsystem performance in network processors with smart packet segmentation. [Citation Graph (, )][DBLP]
    
    
21. 
    Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. [Citation Graph (, )][DBLP]