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JoAnn M. Paul: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. JoAnn M. Paul
    Programmers' views of SoCs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:156-181 [Conf]
  2. JoAnn M. Paul, Christopher M. Eatedali, Donald E. Thomas
    The design context of concurrent computation systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:19-24 [Conf]
  3. JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas
    Frequency interleaving as a codesign scheduling paradigm. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:131-135 [Conf]
  4. JoAnn M. Paul, Donald E. Thomas, Alex Bobrek
    Benchmark-based design strategies for single chip heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:54-59 [Conf]
  5. Donald E. Thomas, JoAnn M. Paul, Simon N. Peffers, Sandra J. Weber
    Peer-based multithreaded executable co-specification. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:105-109 [Conf]
  6. Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas
    Modeling and evaluation of hardware/software designs. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:11-16 [Conf]
  7. JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas
    A codesign virtual machine for hierarchical, balanced hardware/software system modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:390-395 [Conf]
  8. JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas
    Schedulers as model-based design elements in programmable heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:408-411 [Conf]
  9. Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim
    High level cache simulation for heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:287-292 [Conf]
  10. Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas
    Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1144-1149 [Conf]
  11. Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas
    Layered, Multi-Threaded, High-Level Performance Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10954-10959 [Conf]
  12. JoAnn M. Paul, Donald E. Thomas
    A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:522-528 [Conf]
  13. JoAnn M. Paul
    Scenario-Oriented Design for Single Chip Heterogeneous Multiprocesso. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  14. JoAnn M. Paul, Arne J. Suppé, Henele I. Adams, Donald E. Thomas
    Multi-Level Modeling of Software on Hardware in Concurrent Computation. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  15. Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul
    System-Level Modeling of a Network Switch SoC. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:62-67 [Conf]
  16. JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas
    Modeling and simulation of steady state and transient behaviors for emergent SoCs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:262-267 [Conf]
  17. Marlin H. Mickle, JoAnn M. Paul
    Dynamic Communication and Architecture of Parallel Processors. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Systems, 1995, pp:439-442 [Conf]
  18. Marlin H. Mickle, William G. Vogt, JoAnn M. Paul
    The Dynamic Analysis of MIMD Architectures. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Systems, 1995, pp:443-446 [Conf]
  19. JoAnn M. Paul
    What's in a Name. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2006, v:39, n:3, pp:87-89 [Journal]
  20. Marlin H. Mickle, JoAnn M. Paul
    Load Balancing Using Heterogeneous Processors for Continuum Problems on a Mesh. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:39, n:1, pp:66-73 [Journal]
  21. Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe
    Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:684-697 [Journal]
  22. Philip Koopman, Howie Choset, Rajeev Gandhi, Bruce H. Krogh, Diana Marculescu, Priya Narasimhan, JoAnn M. Paul, Ragunathan Rajkumar, Daniel P. Siewiorek, Asim Smailagic, Peter Steenkiste, Donald E. Thomas, Chenxi Wang
    Undergraduate embedded system education at Carnegie Mellon. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:3, pp:500-528 [Journal]
  23. JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy
    High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:431-461 [Journal]
  24. JoAnn M. Paul, Donald E. Thomas, Alex Bobrek
    Scenario-oriented design for single-chip heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:868-880 [Journal]
  25. Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
    Shared Resource Access Attributes for High-Level Contention Models. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:720-725 [Conf]
  26. JoAnn M. Paul, Brett H. Meyer
    Amdahl's Law Revisited for Single Chip Systems. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:2, pp:101-123 [Journal]
  27. Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas
    Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:805-812 [Journal]

  28. Webpage-based benchmarks for mobile device design. [Citation Graph (, )][DBLP]


  29. Event-based re-training of statistical contention models for heterogeneous multiprocessors. [Citation Graph (, )][DBLP]


  30. Holistic design and caching in mobile computing. [Citation Graph (, )][DBLP]


  31. The Emerging Landscape of Computer Performance Evaluation. [Citation Graph (, )][DBLP]


  32. A New Era of Performance Evaluation. [Citation Graph (, )][DBLP]


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