Search the dblp DataBase

Publications of Author

1. Tarvo Raudvere, Ingo Sander, Ashish Kumar Singh, Axel Jantsch
   Verification of design decisions in ForSyDe. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2003, pp:176-181 [Conf]
   
2. Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky
   Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:522-527 [Conf]
   
3. Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch
   Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:690-691 [Conf]
   
4. Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch
   System level verification of digital signal processing applications based on the polynomial abstraction technique. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:285-290 [Conf]
   
5. Ashish Kumar Singh, Murari Mani, Michael Orshansky
   Statistical technology mapping for parametric yield. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:511-518 [Conf]
   
6. Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
   An accurate sparse matrix based framework for statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:231-236 [Conf]
   
7. Murari Mani, Ashish Kumar Singh, Michael Orshansky
   Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:19-26 [Conf]
   
8. Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
   Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. [Citation Graph (0, 0)][DBLP]
   DAC, 2007, pp:148-153 [Conf]
   
9. Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky
   Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies [Citation Graph (0, 0)][DBLP]
   CoRR, 2007, v:0, n:, pp:- [Journal]
   
10. 
    Torpid Mode: Hybrid of Sleep and Idle Mode as Power Saving Mechanism for IEEE 802.16j. [Citation Graph (, )][DBLP]
    
    
11. 
    Mitigation of intra-array SRAM variability using adaptive voltage architecture. [Citation Graph (, )][DBLP]
    
    
12. 
    A Secure and Efficient Multi-authority Proactive Election Scheme. [Citation Graph (, )][DBLP]