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Martti Forsell: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Juha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell
    Fast processor core selection for WLAN modem using mappability estimation. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:61-66 [Conf]
  2. Martti Forsell, Martti Penttonen, Ville Leppänen
    Efficient Two-Level Mesh based Simulation of PRAMs. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1996, pp:29-35 [Conf]
  3. Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani
    A Network on Chip Architecture and Design Methodology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:117-124 [Conf]
  4. Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar
    Extending Platform-Based Design to Network on Chip Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:401-0 [Conf]
  5. Martti Forsell
    MTAC - A Multithreaded VLIW Architecture for PRAM Simulation. [Citation Graph (0, 0)][DBLP]
    J. UCS, 1997, v:3, n:9, pp:1037-1055 [Journal]
  6. Martti Forsell
    A Scalable High-Performance Computing Solution for Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:5, pp:46-55 [Journal]
  7. Eugene I. Ageenko, Martti Forsell, Pasi Fränti
    Context-based compression of binary images in parallel. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 2002, v:32, n:13, pp:1223-1237 [Journal]

  8. HPPC 2007: Workshop on Highly Parallel Processing on a Chip. [Citation Graph (, )][DBLP]

  9. Second Workshop on Highly Parallel Processing on a Chip (HPPC 2008). [Citation Graph (, )][DBLP]

  10. HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? [Citation Graph (, )][DBLP]

  11. HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip. [Citation Graph (, )][DBLP]

  12. On the performance and cost of some PRAM models on CMP hardware. [Citation Graph (, )][DBLP]

  13. Moving Threads: A Non-Conventional Approach for Mapping Computation to MP-SOC. [Citation Graph (, )][DBLP]

  14. Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architectures. [Citation Graph (, )][DBLP]

  15. MTPA - A Processor Architecture for MP-SOCs Employing the Moving Threads Paradigm. [Citation Graph (, )][DBLP]

  16. Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. [Citation Graph (, )][DBLP]

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