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Karsten Strehl: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Karsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    Scheduling hardware/software systems using symbolic techniques. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:173-177 [Conf]
  2. Karsten Strehl, Lothar Thiele
    Interval Diagram Techniques for Symbolic Model Checking of Petri Nets. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:756-757 [Conf]
  3. Christian Haubelt, Marek Jersak, Kai Richter, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich, Lothar Thiele
    SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 2005, pp:693-697 [Conf]
  4. Karsten Strehl, Lothar Thiele
    Symbolic model checking of process networks using interval diagram techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:686-692 [Conf]
  5. Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    FunState - an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:558-565 [Conf]
  6. Karsten Strehl, Claudio Moraga, Karl-Heinz Temme, Radomir S. Stankovic
    Fuzzy Decision Diagrams for the Representation, Analysis and Optimization of Rule Bases. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:127-132 [Conf]
  7. Karsten Strehl
    Interval Diagrams: Increasing Efficiency of Symbolic Real-Time Verification. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1999, pp:488-0 [Conf]
  8. Lothar Thiele, Jürgen Teich, Karsten Strehl
    Regular state machines. [Citation Graph (0, 0)][DBLP]
    Parallel Algorithms Appl., 2000, v:15, n:3-4, pp:265-300 [Journal]
  9. Karsten Strehl, Lothar Thiele
    Interval diagrams for efficient symbolic verification of processnetworks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:939-956 [Journal]
  10. Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    FunState-an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:524-544 [Journal]

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