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Publications of Author

1. Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers
   Design-For-Debug in Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP]
   CODES, 1997, pp:35-42 [Conf]
   
2. Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
   Fault detection and diagnosis with parity trees for space compaction of test responses. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:1095-1098 [Conf]
   
3. A. Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich
   Circuit partitioning for efficient logic BIST synthesis. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:86-91 [Conf]
   
4. Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich
   Impact of Test Point Insertion on Silicon Area and Timing during Layout. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:810-815 [Conf]
   
5. Jeroen Voeten, Harald P. E. Vranken
   Behavior-Preserving Transformations for Design-for-Test. [Citation Graph (0, 0)][DBLP]
   EUROMICRO, 2000, pp:1193-0 [Conf]
   
6. Harald P. E. Vranken, Tomás Garciá Garciá, Sjouke Mauw, Loe M. G. Feijs
   IC Design Validation Using Message Sequence Charts. [Citation Graph (0, 0)][DBLP]
   EUROMICRO, 2000, pp:1122-0 [Conf]
   
7. Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel
   TriMedia CPU64 Architecture. [Citation Graph (0, 0)][DBLP]
   ICCD, 1999, pp:586-592 [Conf]
   
8. Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers
   Efficient Pattern Mapping for Deterministic Logic BIST. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:48-56 [Conf]
   
9. Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen
   Application of deterministic logic BIST on industrial circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 2000, pp:105-114 [Conf]
   
10. Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
    X-Masking During Logic BIST and Its Impact on Defect Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:442-451 [Conf]
    
11. Harald P. E. Vranken, Friedrich Hapke, Soenke Rogge, Domenico Chindamo, Erik H. Volkerink
    ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1069-1078 [Conf]
    
12. Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers, J. H. M. M. van Rhee
    System-Level Testability of Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:134-142 [Conf]
    
13. Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier
    Enhanced reduced pin-count test for full-scan design. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:738-747 [Conf]
    
14. Harald P. E. Vranken, Marc F. Witteman, Ronald C. van Wuijtswinkel
    Design for Testability in Hardware-Software Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:79-87 [Journal]
    
15. 
    Experiences with a synchronous virtual classroom in distance education. [Citation Graph (, )][DBLP]