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M. P. J. Stevens: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers
    Design-For-Debug in Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:35-42 [Conf]
  2. P. H. A. van der Putten, Jeroen Voeten, Marc Geilen, M. P. J. Stevens
    System Level Models for Real-Time Communication. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1496-0 [Conf]
  3. Jeroen Voeten, P. H. A. van der Putten, Marc Geilen, M. P. J. Stevens
    System Level Modelling for Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10154-10161 [Conf]
  4. Jeroen Voeten, P. H. A. van der Putten, M. P. J. Stevens
    Behaviour-Preserving Transformations in SHE: A Formal Approach to Architecture Design. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1996, pp:19-27 [Conf]
  5. Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers, J. H. M. M. van Rhee
    System-Level Testability of Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:134-142 [Conf]
  6. Marc Geilen, Jeroen Voeten, P. H. A. van der Putten, L. J. van Bokhoven, M. P. J. Stevens
    Object-oriented modelling and specification using SHE. [Citation Graph (0, 0)][DBLP]
    Comput. Lang., 2001, v:27, n:1/3, pp:19-38 [Journal]
  7. Bart D. Theelen, A. C. Verschueren, V. V. Reyes Suárez, M. P. J. Stevens, A. Nuñez
    A scalable single-chip multi-processor architecture with on-chip RTOS kernel. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:619-639 [Journal]

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