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Amer Baghdadi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed Amine Jerraya
    A generic wrapper architecture for multi-processor SoC cosimulation and design. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:195-200 [Conf]
  2. Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava
    Component-based design approach for multicore SoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:789-794 [Conf]
  3. Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya
    An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:250-255 [Conf]
  4. Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya
    Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:518-523 [Conf]
  5. Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
    An efficient architecture model for systematic design of application-specific multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:55-63 [Conf]
  6. Olivier Muller, Amer Baghdadi, Michel Jézéquel
    ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1330-1335 [Conf]
  7. Amer Baghdadi, Nacer-Eddine Zergainoh, Damien Lyonnard, Ahmed Amine Jerraya
    Generic Architecture Platform for Multiprocessor System-On-Chip Design. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:53-64 [Conf]
  8. Nacer-Eddine Zergainoh, Amer Baghdadi, Ludovic Tambour, Damien Lyonnard, Lovic Gauthier, Ahmed Amine Jerraya
    Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:99-110 [Conf]
  9. Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, T. Roudier, Ahmed Amine Jerraya
    Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:8-13 [Conf]
  10. Ferid Gharsalli, Amer Baghdadi, Marius Bonaciu, Giedrius Majauskas, Wander O. Cesário, Ahmed Amine Jerraya
    An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:80-87 [Conf]
  11. Arif Sasongko, Amer Baghdadi, Frédéric Rousseau, Ahmed Amine Jerraya
    Embedded Application Prototyping on a Communication-Restricted Reconfigurable. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:33-39 [Conf]
  12. Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
    Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 2002, v:28, n:9, pp:822-831 [Journal]
  13. Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
    Exploration de l'espace des solutions architecturales dans le codesign. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2002, v:21, n:1, pp:9-35 [Journal]
  14. Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel
    Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:654-659 [Conf]
  15. Olivier Muller, Amer Baghdadi, Michel Jézéquel
    On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]

  16. Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. [Citation Graph (, )][DBLP]


  17. ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications. [Citation Graph (, )][DBLP]


  18. Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. [Citation Graph (, )][DBLP]


  19. Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder. [Citation Graph (, )][DBLP]


  20. High-Level System Modeling for Rapid HW/SW Architecture Exploration. [Citation Graph (, )][DBLP]


  21. From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. [Citation Graph (, )][DBLP]


  22. FPGA-based Radar Signal Processing for Automotive Driver Assistance System. [Citation Graph (, )][DBLP]


  23. Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer. [Citation Graph (, )][DBLP]


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