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Chuanjun Zhang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chuanjun Zhang
    An efficient direct mapped instruction cache for application-specific embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:45-50 [Conf]
  2. Chuanjun Zhang, Frank Vahid
    Using a Victim Buffer in an Application-Specific Memory Hierarchy. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:220-227 [Conf]
  3. Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
    A Self-Tuning Cache Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:142-147 [Conf]
  4. Chuanjun Zhang, Jun Yang, Frank Vahid
    Low Static-Power Frequent-Value Data Caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:214-219 [Conf]
  5. Dinesh C. Suresh, Jun Yang, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar
    FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. [Citation Graph (0, 0)][DBLP]
    HiPC, 2003, pp:44-54 [Conf]
  6. Lingling Jin, Wei Wu, Jun Yang, Chuanjun Zhang, Youtao Zhang
    Dynamic Co-allocation of Level One Caches. [Citation Graph (0, 0)][DBLP]
    ICESS, 2005, pp:373-385 [Conf]
  7. Chuanjun Zhang
    Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:155-166 [Conf]
  8. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    A Highly-Configurable Cache Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:136-146 [Conf]
  9. Chuanjun Zhang, Frank Vahid
    A power-configurable bus for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:809-812 [Conf]
  10. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
    A way-halting cache for low-energy high-performance systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:126-131 [Conf]
  11. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    Energy Benefits of a Configurable Line Size Cache for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:87-91 [Conf]
  12. Chuanjun Zhang, Frank Vahid
    Cache Configuration Exploration on Prototyping Platforms. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:164-0 [Conf]
  13. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
    A Way-Halting Cache for Low-Energy High-Performance Systems. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
  14. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
    A way-halting cache for low-energy high-performance systems. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:1, pp:34-54 [Journal]
  15. Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
    A self-tuning cache architecture for embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:407-425 [Journal]
  16. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    A highly configurable cache for low energy embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:2, pp:363-387 [Journal]
  17. Jun Yang, Rajiv Gupta, Chuanjun Zhang
    Frequent value encoding for low power data buses. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:3, pp:354-384 [Journal]
  18. Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt
    Highly configurable platforms for embedded computing systems. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:11, pp:1025-1029 [Journal]

  19. A Low Power Highly Associative Cache for Embedded Systems. [Citation Graph (, )][DBLP]


  20. A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems. [Citation Graph (, )][DBLP]


  21. Reduce Register Files Leakage Through Discharging Cells. [Citation Graph (, )][DBLP]


  22. Two dimensional highly associative level-two cache design. [Citation Graph (, )][DBLP]


  23. Divide-and-conquer: a bubble replacement for low level caches. [Citation Graph (, )][DBLP]


  24. Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses. [Citation Graph (, )][DBLP]


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