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Takashi Yokota: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Takashi Yokota, Kanemitsu Ootsu, Fumihito Furukawa, Takanobu Baba
    Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:309-322 [Conf]
  2. Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba
    A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:307-308 [Conf]
  3. Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba
    Real-Time Medical Diagnosis on a Multiple FPGA-based System. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1088-1091 [Conf]
  4. Atsushi Hori, Takashi Yokota, Yutaka Ishikawa, Shuichi Sakai, Hiroki Konaka, Munenori Maeda, Takashi Tomokiyo, Jörg Nolte, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono
    Time Space Sharing Scheduling and Architectural Support. [Citation Graph (0, 0)][DBLP]
    JSSPP, 1995, pp:92-105 [Conf]
  5. Takashi Yokota, Moriyuki Saito, Fumihito Furukawa, Kanemitsu Ootsu, Takanobu Baba
    Two-Path Limited Speculation Method for Static/Dynamic Optimization in Multithreaded Systems. [Citation Graph (0, 0)][DBLP]
    PDCAT, 2005, pp:46-50 [Conf]
  6. Atsushi Tsukikawa, Fumihito Furukawa, Takayuki Aoki, Daisuke Oka, Tsukikawa, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba
    Design and Implementation of a VLIW Processor Simulation Environment with Instruction Scheduling Framework. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2005, pp:536-541 [Conf]
  7. Kanemitsu Ootsu, Takafumi Ono, Takashi Yokota, Takanobu Baba
    A Methodology of Binary-level Multithreading and Its Preliminary Evaluation. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2002, pp:792-797 [Conf]
  8. Shuichi Sakai, Hiroshi Matsuoka, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota
    RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:122-127 [Conf]
  9. Yoshiyuki Iwamoto, Koichi Suga, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba
    Receiving message prediction method. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2003, v:29, n:11-12, pp:1509-1538 [Journal]
  10. Shuichi Sakai, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hiroshi Matsuoka, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota
    Reduced Interprocessor-Communication Architecture and its Implementation on EM-4. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1995, v:21, n:5, pp:753-769 [Journal]
  11. Kanemitsu Ootsu, Takahiko Kobayashi, Takashi Yokota, Takanobu Baba
    A thread partitioning technique for multithreaded execution along hot paths. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2007, pp:278-282 [Conf]
  12. Takashi Yokota, Masaaki Ogawa, Kanemitsu Ootsu, Takamitsu Baba
    Quasi-global routing for fault-tolerant high-performance interconnection networks. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2007, pp:198-193 [Conf]

  13. Potentials of Branch Predictors: From Entropy Viewpoints. [Citation Graph (, )][DBLP]


  14. Clustered Decoupled Software Pipelining on Commodity CMP. [Citation Graph (, )][DBLP]


  15. An Effective Throttling Method Based on Quasi-global Congestion Information. [Citation Graph (, )][DBLP]


  16. Are Uniform Nerworks Scalable? [Citation Graph (, )][DBLP]


  17. Clustered Software Queue for Efficient Pipelined Multithreading. [Citation Graph (, )][DBLP]


  18. Introducing entropies for representing program behavior and branch predictor performance. [Citation Graph (, )][DBLP]


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