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Publications of Author

1. Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
   Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2006, pp:235-240 [Conf]
   
2. Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naehyuck Chang
   An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors. [Citation Graph (0, 0)][DBLP]
   LCTES/OM, 2001, pp:1-10 [Conf]
   
3. Sheayun Lee, Chang-Gun Lee, Minsuk Lee, Sang Lyul Min, Chong-Sang Kim
   Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems. [Citation Graph (0, 0)][DBLP]
   LCTES, 1998, pp:51-64 [Conf]
   
4. Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson
   Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2003, pp:33-48 [Conf]
   
5. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
   A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2004, pp:244-258 [Conf]
   
6. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
   A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
   WCET, 2003, pp:91-94 [Conf]
   
7. Sheayun Lee, Sang Lyul Min, Chong-Sang Kim, Chang-Gun Lee, Minsuk Lee
   Cache-Conscious Limited Preemptive Scheduling. [Citation Graph (0, 0)][DBLP]
   Real-Time Systems, 1999, v:17, n:2-3, pp:257-282 [Journal]
   
8. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
   Selective code transformation for dual instruction set processors. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]