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Koen Bertels: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Carlo Galuzzi, Elena Moscu Panainte, Yana Yankova, Koen Bertels, Stamatis Vassiliadis
    Automatic selection of application-specific instruction-set extensions. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:160-165 [Conf]
  2. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    Instruction Scheduling for Dynamic Hardware Configurations. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:100-105 [Conf]
  3. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    Compiler-driven FPGA-area allocation for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:369-374 [Conf]
  4. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    Compiling for the Molen Programming Paradigm. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:900-910 [Conf]
  5. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    The PowerPC Backend Molen Compiler. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:434-443 [Conf]
  6. Koen Bertels, Philip Vanneste, Carlos De Backer
    A Cognitive Model of Programming Knowledge for Procedural Languages. [Citation Graph (0, 0)][DBLP]
    ICCAL, 1992, pp:124-135 [Conf]
  7. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    Dynamic Hardware Reconfigurations: Performance Impact for MPEG2. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:284-292 [Conf]
  8. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    Interprocedural Optimization for Dynamic Hardware Configurations. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:2-11 [Conf]
  9. Stamatis Vassiliadis, Georgi Gaydadjiev, Koen Bertels, Elena Moscu Panainte
    The Molen Programming Paradigm. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:1-10 [Conf]
  10. Koen Bertels, Philip Vanneste, Carlos De Backer
    A Cognitive Approach to Program Understanding. [Citation Graph (0, 0)][DBLP]
    WCRE, 1993, pp:1-7 [Conf]
  11. Koen Bertels, L. Neuberg, Stamatis Vassiliadis, D. G. Pechanek
    On Chaos and Neural Networks: The Backpropagation Paradigm. [Citation Graph (0, 0)][DBLP]
    Artif. Intell. Rev., 2001, v:15, n:3, pp:165-187 [Journal]
  12. Koen Bertels, Magnus Boman
    Agent-Based Social Simulation in Markets. [Citation Graph (0, 0)][DBLP]
    Electronic Commerce Research, 2001, v:1, n:1/2, pp:149-158 [Journal]
  13. Koen Bertels, L. Neuberg, Stamatis Vassiliadis, D. G. Pechanek
    Chaos and Neural Network Learning. Some Observations. [Citation Graph (0, 0)][DBLP]
    Neural Processing Letters, 1998, v:7, n:2, pp:69-80 [Journal]
  14. Stamatis Vassiliadis, Sorin Cotofana, Koen Bertels
    2-1 Additions and Related Arithmetic Operations with Threshold Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:9, pp:1062-1067 [Journal]
  15. Stamatis Vassiliadis, Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte
    The MOLEN Polymorphic Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1363-1375 [Journal]
  16. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    The Molen compiler for reconfigurable processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:1, pp:- [Journal]
  17. B. Pourebrahimi, Koen Bertels, G. M. Kandru, Stamatis Vassiliadis
    Market-Based Resource Allocation in Grids. [Citation Graph (0, 0)][DBLP]
    e-Science, 2006, pp:80- [Conf]
  18. Yana Yankova, Koen Bertels, Stamatis Vassiliadis, Roel Meeuws, Arcilio Virginia
    Automated HDL Generation: Comparative Evaluation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2750-2753 [Conf]
  19. Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis
    A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:283-293 [Conf]
  20. Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis
    A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:130-141 [Conf]
  21. Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz
    PISC: Polymorphic Instruction Set Computers. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:274-286 [Conf]
  22. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:161-172 [Journal]

  23. A Dynamic Pricing and Bidding Strategy for Autonomous Agents in Grids. [Citation Graph (, )][DBLP]


  24. Hybrid Resource Discovery Mechanism in Ad Hoc Grid Using Structured Overlay. [Citation Graph (, )][DBLP]


  25. Effect of the Degree of Neighborhood on Resource Discovery in Ad Hoc Grids. [Citation Graph (, )][DBLP]


  26. An efficient algorithm for free resources management on the FPGA. [Citation Graph (, )][DBLP]


  27. Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems. [Citation Graph (, )][DBLP]


  28. Toward a runtime system for reconfigurable computers: A virtualization approach. [Citation Graph (, )][DBLP]


  29. Algorithms for the automatic extension of an instruction-set. [Citation Graph (, )][DBLP]


  30. Evaluation of runtime task mapping heuristics with rSesame - a case study. [Citation Graph (, )][DBLP]


  31. Acceleration of Smith-Waterman using Recursive Variable Expansion. [Citation Graph (, )][DBLP]


  32. Data path Configuration Time Reduction for Run-time Reconfigurable Systems. [Citation Graph (, )][DBLP]


  33. Auction Protocols for Resource Allocations in Ad-Hoc Grids. [Citation Graph (, )][DBLP]


  34. A clustering framework for task partitioning based on function-level data usage analysis. [Citation Graph (, )][DBLP]


  35. MORPHEUS: Heterogeneous Reconfigurable Computing. [Citation Graph (, )][DBLP]


  36. HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. [Citation Graph (, )][DBLP]


  37. Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform. [Citation Graph (, )][DBLP]


  38. DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator. [Citation Graph (, )][DBLP]


  39. A Quantitative Prediction Model for Hardware/Software Partitioning. [Citation Graph (, )][DBLP]


  40. Loop unrolling and shifting for reconfigurable architectures. [Citation Graph (, )][DBLP]


  41. Compiler assisted runtime task scheduling on a reconfigurable computer. [Citation Graph (, )][DBLP]


  42. Ant Colony Inspired Microeconomic Based Resource Management in Ad Hoc Grids. [Citation Graph (, )][DBLP]


  43. A self-adaptive on-line task placement algorithm for partially reconfigurable systems. [Citation Graph (, )][DBLP]


  44. Runtime decision of hardware or software execution on a heterogeneous reconfigurable platform. [Citation Graph (, )][DBLP]


  45. Flexible pipelining design for recursive variable expansion. [Citation Graph (, )][DBLP]


  46. System-level runtime mapping exploration of reconfigurable architectures. [Citation Graph (, )][DBLP]


  47. hArtes design flow for heterogeneous platforms. [Citation Graph (, )][DBLP]


  48. Fair access to scarce resources in ad-hoc grids using an economic-based approach. [Citation Graph (, )][DBLP]


  49. A Two-phase Practical Parallel Algorithm for Construction of Huffman Codes. [Citation Graph (, )][DBLP]


  50. System-Level Design Space Exploration of Dynamic Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  51. Clustering method for the identification of convex disconnected Multiple Input Multiple Output instructions. [Citation Graph (, )][DBLP]


  52. Performance Evaluation of Real-Time Message Delivery in RDM Algorithm. [Citation Graph (, )][DBLP]


  53. Optimal Unroll Factor for Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  54. A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  55. Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices. [Citation Graph (, )][DBLP]


  56. The Instruction-Set Extension Problem: A Survey. [Citation Graph (, )][DBLP]


  57. Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems. [Citation Graph (, )][DBLP]


  58. QUAD - A Memory Access Pattern Analyser. [Citation Graph (, )][DBLP]


  59. 3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices. [Citation Graph (, )][DBLP]


  60. Market Formulation for Resources Allocation in an Ad-Hoc Grid. [Citation Graph (, )][DBLP]


  61. Self-Organizing Dynamic Ad Hoc Grids. [Citation Graph (, )][DBLP]


  62. Resource Discovery with Dynamic Matchmakers in Ad Hoc Grid. [Citation Graph (, )][DBLP]


  63. Resource Allocation in Market-based Grids Using a History-based Pricing Mechanism. [Citation Graph (, )][DBLP]


  64. Adaptation to Dynamic Resource Availability in Ad Hoc Grids through a Learning Mechanism. [Citation Graph (, )][DBLP]


  65. A Multipurpose Clustering Algorithm for Task Partitioning in Multicore Reconfigurable Systems. [Citation Graph (, )][DBLP]


  66. Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform. [Citation Graph (, )][DBLP]


  67. A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements. [Citation Graph (, )][DBLP]


  68. Automatic Instruction-Set Extensions with the Linear Complexity Spiral Search. [Citation Graph (, )][DBLP]


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