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Arun Kejariwal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkarmark, Xinmin Tian, Hideki Saito
    Challenges in exploitation of loop parallelism in embedded applications. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:173-180 [Conf]
  2. Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta
    Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:556-561 [Conf]
  3. Ana Azevedo, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau
    High performance annotation-aware JVM for Java cards. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:52-61 [Conf]
  4. Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta
    Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:33-38 [Conf]
  5. Milind Girkar, Arun Kejariwal, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos
    Probablistic Self-Scheduling. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:253-264 [Conf]
  6. Arun Kejariwal, Alexandru Nicolau, Constantine D. Polychronopoulos
    History-aware Self-Scheduling. [Citation Graph (0, 0)][DBLP]
    ICPP, 2006, pp:185-192 [Conf]
  7. Arun Kejariwal, Xinmin Tian, Wei Li, Milind Girkar, Sergey Kozhukhov, Hideki Saito, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos
    On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:24- [Conf]
  8. Arun Kejariwal, Hideki Saito, Xinmin Tian, Milind Girkar, Wei Li, Utpal Banerjee, Alexandru Nicolau, Constantine D. Polychronopoulos
    Lightweight lock-free synchronization methods for multithreading. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:361-371 [Conf]
  9. Arun Kejariwal, Alexandru Nicolau
    An Efficient Load Balancing Scheme for Grid-based High Performance Scientific Computing. [Citation Graph (0, 0)][DBLP]
    ISPDC, 2005, pp:217-225 [Conf]
  10. Arun Kejariwal, Paolo D'Alberto, Alexandru Nicolau, Constantine D. Polychronopoulos
    A Geometric Approach for Partitioning N-Dimensional Non-rectangular Iteration Spaces. [Citation Graph (0, 0)][DBLP]
    LCPC, 2004, pp:102-116 [Conf]
  11. Arun Kejariwal, Alexandru Nicolau, Constantine D. Polychronopoulos
    An Efficient Approach for Self-scheduling Parallel Loops on Multiprogrammed Parallel Computers. [Citation Graph (0, 0)][DBLP]
    LCPC, 2005, pp:441-449 [Conf]
  12. Arun Kejariwal, Alexandru Nicolau, Utpal Banerjee, Constantine D. Polychronopoulos
    A novel approach for partitioning iteration spaces with variable densities. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2005, pp:120-131 [Conf]
  13. Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li, Sergey Kozhukhov, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos
    Tight analysis of the performance potential of thread speculation using spec CPU 2006. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:215-225 [Conf]
  14. Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar
    Rapid Resource-Constrained Hardware Performance Estimation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:40-46 [Conf]
  15. Prabhat Mishra, Arun Kejariwal, Nikil Dutt
    Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:226-232 [Conf]
  16. Arun Kejariwal, Alexandru Nicolau, Hideki Saito, Xinmin Tian, Milind Girkar, Utpal Banerjee, Constantine D. Polychronopoulos
    A general approach for partitioning N-dimensional parallel nested loops with conditionals. [Citation Graph (0, 0)][DBLP]
    SPAA, 2006, pp:49-58 [Conf]
  17. Prabhat Mishra, Arun Kejariwal, Nikil Dutt
    Synthesis-driven Exploration of Pipelined Embedded Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:921-926 [Conf]
  18. Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil D. Dutt, Rajesh K. Gupta
    Energy efficient watermarking on mobile devices using proxy-based partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:625-636 [Journal]
  19. Gerolf Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum
    Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2007, pp:361-362 [Conf]
  20. Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau
    A predictive decode filter cache for reducing power consumption in embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]

  21. Exploitation of nested thread-level speculative parallelism on multi-core systems. [Citation Graph (, )][DBLP]


  22. Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems. [Citation Graph (, )][DBLP]


  23. Synchronization optimizations for efficient execution on multi-cores. [Citation Graph (, )][DBLP]


  24. Compiler-Driven Dependence Profiling to Guide Program Parallelization. [Citation Graph (, )][DBLP]


  25. Cache-aware iteration space partitioning. [Citation Graph (, )][DBLP]


  26. Techniques for efficient placement of synchronization primitives. [Citation Graph (, )][DBLP]


  27. Parallelization spectroscopy: analysis of thread-level parallelism in hpc programs. [Citation Graph (, )][DBLP]


  28. Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor. [Citation Graph (, )][DBLP]


  29. On the efficacy of call graph-level thread-level speculation. [Citation Graph (, )][DBLP]


  30. Performance Characterization of Itanium® 2-Based Montecito Processor. [Citation Graph (, )][DBLP]


  31. Cache-aware partitioning of multi-dimensional iteration spaces. [Citation Graph (, )][DBLP]


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