The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Junchao Zhang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Feng Zhou, Junchao Zhang, Chengyong Wu, Zhaoqing Zhang
    A Register Allocation Framework for Banked Register Files with Access Constraints. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:269-280 [Conf]
  2. Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang, Huimin Cui, Dongrui Fan
    Optimized Register Renaming Scheme for Stack-Based x86 Operations. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:43-56 [Conf]
  3. Chengyong Wu, Ruiqi Lian, Junchao Zhang, Roy Ju, Sun Chan, Lixia Liu, Xiaobing Feng 0002, Zhaoqing Zhang
    An Overview of the Open Research Compiler. [Citation Graph (0, 0)][DBLP]
    LCPC, 2004, pp:17-31 [Conf]
  4. Xuehai Qian, He Huang, Hao Zhang, Guoping Long, Junchao Zhang, Dongrui Fan
    Design and Implementation of Floating Point Stack on General RISC Architecture. [Citation Graph (0, 0)][DBLP]
    PDP, 2007, pp:238-245 [Conf]
  5. Xuehai Qian, Hao Zhang, Jingang Yang, He Huang, Junchao Zhang, Dongrui Fan
    Circuit implementation of floating point range reduction for trigonometric functions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3010-3013 [Conf]

  6. Software and Hardware Cooperate for 1-D FFT Algorithm Optimization on Multicore Processors. [Citation Graph (, )][DBLP]


  7. Design of New Hash Mapping Functions. [Citation Graph (, )][DBLP]


  8. A Performance Model of Dense Matrix Operations on Many-Core Architectures. [Citation Graph (, )][DBLP]


  9. Characterizing and Understanding the Bandwidth Behavior of Workloads on Multi-core Processors. [Citation Graph (, )][DBLP]


  10. High Performance Matrix Multiplication on Many Cores. [Citation Graph (, )][DBLP]


  11. Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture. [Citation Graph (, )][DBLP]


  12. Experience on optimizing irregular computation for memory hierarchy in manycore architecture. [Citation Graph (, )][DBLP]


  13. Architectural support for cilk computations on many-core architectures. [Citation Graph (, )][DBLP]


  14. Study on Fine-Grained Synchronization in Many-Core Architecture. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.003secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002