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Publications of Author

1. Hiroshi Makino, Makoto Kizawa
   An Automatic Translation System Of Non-Segmented Kana Sentences Into Kanji-Kana Sentences. [Citation Graph (0, 0)][DBLP]
   COLING, 1980, pp:295-302 [Conf]
   
2. Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
   Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:398-405 [Conf]
   
3. Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara
   A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. [Citation Graph (0, 0)][DBLP]
   ICCD, 1993, pp:202-205 [Conf]
   
4. Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano
   A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. [Citation Graph (0, 0)][DBLP]
   ICCD, 1997, pp:685-689 [Conf]
   
5. Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino
   A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2005, pp:73-76 [Conf]
   
6. Koji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano
   A low power SRAM using auto-backgate-controlled MT-CMOS. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1998, pp:293-298 [Conf]
   
7. 
   Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. [Citation Graph (, )][DBLP]