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Dinesh P. Mehta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dinesh P. Mehta, Vijay Raghavan
    Decision Tree Approximations of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    COLT, 2000, pp:16-24 [Conf]
  2. Dinesh P. Mehta, Sartaj Sahni
    Computing Display Conflicts in String and Circular String Visualization. [Citation Graph (0, 0)][DBLP]
    CPM, 1992, pp:244-261 [Conf]
  3. Mario A. Lopez, Dinesh P. Mehta
    Partitioning Algorithms for Corner Stitching. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:200-0 [Conf]
  4. Dinesh P. Mehta, Naveed A. Sherwani
    A Minimum-Area Floorplanning Algorithm for MBC Designs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:56-59 [Conf]
  5. Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang
    Constrained "Modern" Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:128-135 [Conf]
  6. Yan Feng, Dinesh P. Mehta
    Constrained Floorplanning with Whitespace. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:969-974 [Conf]
  7. Yan Feng, Dinesh P. Mehta
    Heterogeneous Floorplanning for FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:257-262 [Conf]
  8. Kun Gao, Dinesh P. Mehta
    Floorplan Classification Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:975-980 [Conf]
  9. Dinesh P. Mehta, Naveed A. Sherwani, A. Bariya
    T3: Physical Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:3-0 [Conf]
  10. Dinesh P. Mehta, Erica D. Wilson
    Parallel algorithms for corner stitching. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 1998, v:10, n:15, pp:1317-1341 [Journal]
  11. Sahar Idwan, Dinesh P. Mehta, Mario A. Lopez
    Fast Pursuit Of Mobile Nodes Using TPR Trees. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2004, v:15, n:5, pp:753-772 [Journal]
  12. Dinesh P. Mehta, Sartaj K. Sahni
    Models, techniques, and algorithms for finding, selecting, and displaying patterns in strings and other discrete objects. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 1997, v:39, n:3, pp:201-221 [Journal]
  13. Krishna M. Kavi, Dinesh P. Mehta
    Mutual Exclusion on Optical Buses. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 2002, v:12, n:3-4, pp:341-358 [Journal]
  14. Dinesh P. Mehta, Sartaj Sahni
    A Data Structure for Circular String Analysis and Visualization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:8, pp:992-997 [Journal]
  15. Dinesh P. Mehta, Sartaj Sahni
    Computing Display Conflicts in String Visualization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:3, pp:350-361 [Journal]
  16. Yan Feng, Dinesh P. Mehta
    Module relocation to obtain feasible constrained floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:856-866 [Journal]
  17. Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang
    Constrained floorplanning using network flows. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:572-580 [Journal]
  18. Dinesh P. Mehta, George Blust
    Corner stitching for simple rectilinear shapes [VLSI layouts]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:2, pp:186-198 [Journal]
  19. Dinesh P. Mehta, Vijay Raghavan
    Decision tree approximations of Boolean functions. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2002, v:270, n:1-2, pp:609-623 [Journal]
  20. Brad Williams, Dinesh P. Mehta, Tracy Camp, William Navidi
    Predictive Models to Rebroadcast in Mobile Ad Hoc Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Mob. Comput., 2004, v:3, n:3, pp:295-303 [Journal]
  21. Swanwa Liao, Mario A. Lopez, Dinesh P. Mehta
    Constrained polygon transformations for incremental floorplanning. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:3, pp:322-342 [Journal]
  22. Mario A. Lopez, Dinesh P. Mehta
    Efficient decomposition of polygons into L-shapes with application to VLSI layouts. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:3, pp:371-395 [Journal]
  23. Dinesh P. Mehta
    Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:272-284 [Journal]
  24. Dinesh P. Mehta, Naveed A. Sherwani
    On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:1, pp:82-97 [Journal]

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