|
Search the dblp DataBase
Hsin-Chou Chi:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Hsin-Chou Chi, Yuval Tamir
Starvation Prevention for Arbiters of Crossbars with Multi-Queue Input Buffers. [Citation Graph (0, 0)][DBLP] COMPCON, 1994, pp:292-297 [Conf]
- Hsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu
A Switch Supporting Circuit and Packet Switching for On-Chip Networks. [Citation Graph (0, 0)][DBLP] DDECS, 2006, pp:226-227 [Conf]
- Hsin-Chou Chi, Chia-Ming Wu
Efficient Switches for Network-on-Chip Based Embedded Systems. [Citation Graph (0, 0)][DBLP] EUC, 2005, pp:67-76 [Conf]
- Hsin-Chou Chi, Yuval Tamir
Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers. [Citation Graph (0, 0)][DBLP] ICCD, 1991, pp:233-238 [Conf]
- Hsin-Chou Chi, Chih-Tsung Tang
A Deadlock-Free Routing Scheme for Interconnection Networks with Irregular Topologies. [Citation Graph (0, 0)][DBLP] ICPADS, 1997, pp:88-95 [Conf]
- Hsin-Chou Chi, Wen-Jen Wu
Routing Tree Construction for Interconnection Network with Irregular Topologies. [Citation Graph (0, 0)][DBLP] PDP, 2003, pp:157-164 [Conf]
- Yuval Tamir, Hsin-Chou Chi
Symmetric Crossbar Arbiters for VLSI Communication Switches. [Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:1, pp:13-27 [Journal]
- Hsin-Chou Chi, Chia-Ming Wu
An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP] VLSI-SoC, 2006, pp:68-73 [Conf]
Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures. [Citation Graph (, )][DBLP]
Search in 0.002secs, Finished in 0.002secs
|