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Raghu Sastry: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Albert Mu, Jeff Larson, Raghu Sastry, Thomas Wicki, Winfried W. Wilcke
    A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1996, pp:261-266 [Conf]
  2. Raghu Sastry, N. Ranganathan
    A VLSI Architecture for Computer the Tree-to-Tree Distance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:330-339 [Conf]
  3. N. Ranganathan, Raghu Sastry, R. Venkatesan, Joseph W. Yoder, David C. Keezer
    SMAC: A Scene Matching Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:184-187 [Conf]
  4. Raghu Sastry, N. Ranganathan
    A Systolic Array for Approximate String Matching. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:402-405 [Conf]
  5. Raghu Sastry, N. Ranganathan, Ramesh Jain
    VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:700-704 [Conf]
  6. Raghu Sastry, N. Ranganathan, Horst Bunke
    Hardware Algorithms for Polygon Matching. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:41-44 [Conf]
  7. N. Ranganathan, Raghu Sastry
    VLSI Architectures for Pattern Matching. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1994, v:8, n:4, pp:815-843 [Journal]
  8. Raghu Sastry, N. Ranganathan
    PMAC: A Polygon Matching Chip. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:367-385 [Journal]
  9. Raghu Sastry, N. Ranganathan, Ramesh Jain
    VLSI Architectures for High-Speed Range Estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1995, v:17, n:9, pp:894-899 [Journal]
  10. Raghu Sastry, N. Ranganathan, Klinton Remedios
    CASM: A VLSI Chip for Approximate String Matching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1995, v:17, n:8, pp:824-830 [Journal]
  11. N. Ranganathan, Raghu Sastry, R. Venkatesan
    SMAC: A VLSI Architecture for Scene Matching. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1998, v:4, n:3, pp:171-180 [Journal]
  12. Raghu Sastry, N. Ranganathan
    A VLSI Architecture for Approximate Tree Matching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:3, pp:346-352 [Journal]
  13. Raghu Sastry, N. Ranganathan, Horst Bunke
    VLSI architectures for polygon recognition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:398-407 [Journal]

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