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Andrew R. Pleszkun: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson
    Features of the Structured Memory Access (SMA) Architecture. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1986, pp:259-265 [Conf]
  2. George E. Bier, Andrew R. Pleszkun
    An algorithm for design rule checking on a multiprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:299-304 [Conf]
  3. Andrew R. Pleszkun, Edward S. Davidson
    Structured Memory Access Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP, 1983, pp:461-471 [Conf]
  4. Matthew K. Farrens, Andrew R. Pleszkun
    Improving Performance of Small On-Chip Instruction Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:234-241 [Conf]
  5. Matthew K. Farrens, Andrew R. Pleszkun
    Strategies for Achieving Improved Processor Throughput. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:362-369 [Conf]
  6. Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun
    A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:338-347 [Conf]
  7. James R. Goodman, Jian-tu Hsieh, Koujuch Liou, Andrew R. Pleszkun, P. B. Schechter, Honesty C. Young
    PIPE: A VLSI Decoupled Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:20-27 [Conf]
  8. Dirk Grunwald, Artur Klauser, Srilatha Manne, Andrew R. Pleszkun
    Confidence Estimation for Speculation Control. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:122-131 [Conf]
  9. Andrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter
    WISQ: A Restartable Architecture Using Queues. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:290-299 [Conf]
  10. Andrew R. Pleszkun, Gurindar S. Sohi
    The Performance Potential of Multiple Functional Unit Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:37-44 [Conf]
  11. Andrew R. Pleszkun, Matthew Thazhuthaveetil
    An Architecture for Efficient Lisp List Access. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:191-198 [Conf]
  12. James E. Smith, Andrew R. Pleszkun
    Implementation of Precise Interrupts in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:36-44 [Conf]
  13. James E. Smith, Andrew R. Pleszkun
    Implementation of Precise Interupts in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:291-299 [Conf]
  14. Matthew K. Farrens, Andrew R. Pleszkun
    An evaluation of functional unit lengths for single-chip processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1990, pp:209-215 [Conf]
  15. Andrew R. Pleszkun
    Techniques for compressing program address traces. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:32-39 [Conf]
  16. Andrew R. Pleszkun, Gurindar S. Sohi
    Multiple instruction issue and single-chip processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:64-66 [Conf]
  17. Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
    A modified approach to data cache management. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:93-103 [Conf]
  18. Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun
    MISC: a Multiple Instruction Stream Computer. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:193-196 [Conf]
  19. Stephen Aiken, Dirk Grunwald, Andrew R. Pleszkun, Jesse Willek
    A Performance Analysis of the iSCSI Protocol. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Mass Storage Systems, 2003, pp:123-134 [Conf]
  20. Matthew K. Farrens, Andrew R. Pleszkun
    Implementation of the PIPE Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:1, pp:65-69 [Journal]
  21. Andrew R. Pleszkun, Matthew Thazhuthaveetil
    The Architecture of Lisp Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1987, v:20, n:3, pp:35-44 [Journal]
  22. Matthew Thazhuthaveetil, Andrew R. Pleszkun
    On the Structural Locality of Reference in LISP List Access Streams. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1987, v:26, n:2, pp:105-110 [Journal]
  23. James E. Smith, Andrew R. Pleszkun
    Implementing Precise Interrupts in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:5, pp:562-573 [Journal]

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