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## Search the dblp DataBase
V. Visvanathan:
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## Publications of Author- V. Visvanathan, Linda S. Milor
**An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation.**[Citation Graph (0, 0)][DBLP] Symposium on Computational Geometry, 1986, pp:207-215 [Conf] - A. P.-C. Ng, V. Visvanathan
**A Framework for Scheduling Multi-Rate Circuit Simulation.**[Citation Graph (0, 0)][DBLP] DAC, 1989, pp:19-24 [Conf] - P. Sadayappan, V. Visvanathan
**Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers.**[Citation Graph (0, 0)][DBLP] DAC, 1989, pp:13-18 [Conf] - Pradip Mandal, V. Visvanathan
**Macromodeling of the A.C. characteristics of CMOS Op-amps.**[Citation Graph (0, 0)][DBLP] ICCAD, 1993, pp:334-340 [Conf] - Avinash K. Gautam, V. Visvanathan, S. K. Nandy
**Automatic Generation of Tree Multipliers Using Placement-Driven Netlists.**[Citation Graph (0, 0)][DBLP] ICCD, 1999, pp:285-288 [Conf] - Kalluri Eswar, P. Sadayappan, Chua-Huang Huang, V. Visvanathan
**Supernodal Sparse Cholesky Facotrization on Distributed-Memory Multiprocessors.**[Citation Graph (0, 0)][DBLP] ICPP, 1993, pp:18-22 [Conf] - Kalluri Eswar, P. Sadayappan, V. Visvanathan
**Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors.**[Citation Graph (0, 0)][DBLP] ICPP (3), 1991, pp:159-166 [Conf] - S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan
**A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array.**[Citation Graph (0, 0)][DBLP] ICPP, 1993, pp:94-97 [Conf] - P. Sadayappan, V. Visvanathan
**Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor.**[Citation Graph (0, 0)][DBLP] ICS, 1988, pp:254-265 [Conf] - Sreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan
**A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries.**[Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:530-535 [Conf] - V. K. Anuradha, V. Visvanathan
**A CORDIC Based Programmable DXT Processor Array.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1994, pp:343-348 [Conf] - Sreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney
**Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:336-341 [Conf] - A. Ratan Gupta, V. Visvanathan
**VLSI Implementation of DSP Architectures.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1996, pp:3- [Conf] - Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan
**NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1993, pp:341-346 [Conf] - A. Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal
**High Speed Digital Filtering on SRAM-Based FPGAs.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1994, pp:229-232 [Conf] - Pradip Mandal, V. Visvanathan
**Design of high performance two stage CMOS cascode op-amps with stable biasing.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1996, pp:234-237 [Conf] - Pradip Mandal, V. Visvanathan
**A Self-Biased High Performance Folded Cascode CMOS Op-Amp.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1997, pp:429-434 [Conf] - Pradip Mandal, V. Visvanathan
**A New Approach for CMOS Op-Amp Synthesis.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:189-195 [Conf] - S. Ramanathan, Nibedita Mohanty, V. Visvanathan
**A Methodology for Generating Application Specific Tree Multipliers.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1993, pp:176-179 [Conf] - S. Ramanathan, V. Visvanathan
**A systolic architecture for LMS adaptive filtering with minimal adaptation delay.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1996, pp:286-289 [Conf] - S. Ramanathan, V. Visvanathan
**Low-Power Configurable Processor Array for DLMS Adaptive Filtering.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1997, pp:198-207 [Conf] - S. Ramanathan, V. Visvanathan, S. K. Nandy
**Synthesis of Configurable Architectures for DSP Algorithms.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:350-357 [Conf] - Dinesh Somasekhar, V. Visvanathan
**A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1993, pp:347-350 [Conf] - B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni
**Application of Alpha Power Law Models to PLL Design Methodology.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:768-773 [Conf] - V. Visvanathan, Nibedita Mohanty, S. Ramanathan
**An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1993, pp:166-171 [Conf] - V. Visvanathan, S. Ramanathan
**A modular systolic architecture for delayed least mean squares adaptive filtering.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1995, pp:332-337 [Conf] - S. Ramanathan, V. Visvanathan
**Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1.**[Citation Graph (0, 0)][DBLP] Integration, 1999, v:27, n:1, pp:1-32 [Journal] - S. Ramanathan, V. Visvanathan, S. K. Nandy
**Synthesis of ASIPs for DSP algorithms.**[Citation Graph (0, 0)][DBLP] Integration, 1999, v:28, n:1, pp:13-32 [Journal] - P. Sadayappan, V. Visvanathan
**Circuit Simulation on Shared-Memory Multiprocessors.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1988, v:37, n:12, pp:1634-1642 [Journal] - Richard Saeks, Alberto L. Sangiovanni-Vincentelli, V. Visvanathan
**Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1981, v:30, n:11, pp:899-904 [Journal] - V. Visvanathan, Alberto L. Sangiovanni-Vincentelli
**Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1981, v:30, n:11, pp:889-898 [Journal] - Pradip Mandal, V. Visvanathan
**CMOS op-amp sizing using a geometric programming formulation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:22-38 [Journal] - Linda S. Milor, V. Visvanathan
**Detection of catastrophic faults in analog integrated circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:114-130 [Journal] - P. Sadayappan, V. Visvanathan
**Efficient sparse matrix factorization for circuit simulation on vector supercomputers.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1276-1285 [Journal] - V. Visvanathan, Alberto L. Sangiovanni-Vincentelli
**A Computational Approach for the Diagnosability of Dynamical Circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:165-171 [Journal] - Dinesh Somasekhar, V. Visvanathan
**A 230-MHz half-bit level pipelined multiplier using true single-phase clocking.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:415-422 [Journal]
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