The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
V. Visvanathan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. V. Visvanathan, Linda S. Milor
    An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation. [Citation Graph (0, 0)][DBLP]
    Symposium on Computational Geometry, 1986, pp:207-215 [Conf]
  2. A. P.-C. Ng, V. Visvanathan
    A Framework for Scheduling Multi-Rate Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:19-24 [Conf]
  3. P. Sadayappan, V. Visvanathan
    Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:13-18 [Conf]
  4. Pradip Mandal, V. Visvanathan
    Macromodeling of the A.C. characteristics of CMOS Op-amps. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:334-340 [Conf]
  5. Avinash K. Gautam, V. Visvanathan, S. K. Nandy
    Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:285-288 [Conf]
  6. Kalluri Eswar, P. Sadayappan, Chua-Huang Huang, V. Visvanathan
    Supernodal Sparse Cholesky Facotrization on Distributed-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:18-22 [Conf]
  7. Kalluri Eswar, P. Sadayappan, V. Visvanathan
    Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1991, pp:159-166 [Conf]
  8. S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan
    A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:94-97 [Conf]
  9. P. Sadayappan, V. Visvanathan
    Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICS, 1988, pp:254-265 [Conf]
  10. Sreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan
    A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:530-535 [Conf]
  11. V. K. Anuradha, V. Visvanathan
    A CORDIC Based Programmable DXT Processor Array. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:343-348 [Conf]
  12. Sreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney
    Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:336-341 [Conf]
  13. A. Ratan Gupta, V. Visvanathan
    VLSI Implementation of DSP Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:3- [Conf]
  14. Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan
    NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:341-346 [Conf]
  15. A. Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal
    High Speed Digital Filtering on SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:229-232 [Conf]
  16. Pradip Mandal, V. Visvanathan
    Design of high performance two stage CMOS cascode op-amps with stable biasing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:234-237 [Conf]
  17. Pradip Mandal, V. Visvanathan
    A Self-Biased High Performance Folded Cascode CMOS Op-Amp. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:429-434 [Conf]
  18. Pradip Mandal, V. Visvanathan
    A New Approach for CMOS Op-Amp Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:189-195 [Conf]
  19. S. Ramanathan, Nibedita Mohanty, V. Visvanathan
    A Methodology for Generating Application Specific Tree Multipliers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:176-179 [Conf]
  20. S. Ramanathan, V. Visvanathan
    A systolic architecture for LMS adaptive filtering with minimal adaptation delay. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:286-289 [Conf]
  21. S. Ramanathan, V. Visvanathan
    Low-Power Configurable Processor Array for DLMS Adaptive Filtering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:198-207 [Conf]
  22. S. Ramanathan, V. Visvanathan, S. K. Nandy
    Synthesis of Configurable Architectures for DSP Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:350-357 [Conf]
  23. Dinesh Somasekhar, V. Visvanathan
    A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:347-350 [Conf]
  24. B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni
    Application of Alpha Power Law Models to PLL Design Methodology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:768-773 [Conf]
  25. V. Visvanathan, Nibedita Mohanty, S. Ramanathan
    An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:166-171 [Conf]
  26. V. Visvanathan, S. Ramanathan
    A modular systolic architecture for delayed least mean squares adaptive filtering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:332-337 [Conf]
  27. S. Ramanathan, V. Visvanathan
    Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:27, n:1, pp:1-32 [Journal]
  28. S. Ramanathan, V. Visvanathan, S. K. Nandy
    Synthesis of ASIPs for DSP algorithms. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:28, n:1, pp:13-32 [Journal]
  29. P. Sadayappan, V. Visvanathan
    Circuit Simulation on Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:12, pp:1634-1642 [Journal]
  30. Richard Saeks, Alberto L. Sangiovanni-Vincentelli, V. Visvanathan
    Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:11, pp:899-904 [Journal]
  31. V. Visvanathan, Alberto L. Sangiovanni-Vincentelli
    Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:11, pp:889-898 [Journal]
  32. Pradip Mandal, V. Visvanathan
    CMOS op-amp sizing using a geometric programming formulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:22-38 [Journal]
  33. Linda S. Milor, V. Visvanathan
    Detection of catastrophic faults in analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:114-130 [Journal]
  34. P. Sadayappan, V. Visvanathan
    Efficient sparse matrix factorization for circuit simulation on vector supercomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1276-1285 [Journal]
  35. V. Visvanathan, Alberto L. Sangiovanni-Vincentelli
    A Computational Approach for the Diagnosability of Dynamical Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:165-171 [Journal]
  36. Dinesh Somasekhar, V. Visvanathan
    A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:415-422 [Journal]

Search in 0.004secs, Finished in 0.005secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002