The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Ki-Wook Kim: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ki-Wook Kim, Ki-Byoung Kim, Hyoung-Joo Kim
    VIRON: An Annotation-Based Video Information Retrieval System. [Citation Graph (0, 0)][DBLP]
    COMPSAC, 1996, pp:298-0 [Conf]
  2. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Low-swing clock domino logic incorporating dual supply and dual threshold voltages. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:467-472 [Conf]
  3. Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
    Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:732-737 [Conf]
  4. Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang
    Domino logic synthesis minimizing crosstalk. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:280-285 [Conf]
  5. Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang
    VeriCDF: a new verification methodology for charged device failures. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:874-879 [Conf]
  6. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:260-267 [Conf]
  7. Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
    Logic Transformation for Low Power Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:158-162 [Conf]
  8. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Transistor sizing for reliable domino logic design in dual threshold voltage technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:133-138 [Conf]
  9. Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. (Dave) Liu, Sung-Mo Kang
    Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:318-321 [Conf]
  10. Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
    Implication graph based domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:111-114 [Conf]
  11. Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
    Coupling-aware high-level interconnect synthesis for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:609-613 [Conf]
  12. Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang
    Coupling-aware minimum delay optimization for domino logic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:371-374 [Conf]
  13. Chulwoo Kim, Kiwook Kim, Sung-Mo Kang
    Energy-efficient skewed static logic design with dual Vt. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:882-885 [Conf]
  14. Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang
    Skew-tolerant high-speed (STHS) domino logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:154-157 [Conf]
  15. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Noise constrained power optimization for dual VT domino logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:158-161 [Conf]
  16. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
    Noise-aware power optimization for on-chip interconnect. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:108-113 [Conf]
  17. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Optimal Timing for Skew-Tolerant High-Speed Domino Logic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:41-46 [Conf]
  18. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Timing constraints for domino logic gates with timing-dependent keepers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:96-103 [Journal]
  19. Ki-Wook Kim, Sung-Mo Kang
    Crosstalk noise minimization in domino logic design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1091-1100 [Journal]
  20. Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang
    Domino logic synthesis based on implication graph. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:232-240 [Journal]
  21. Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
    Chip-level charged-device modeling and simulation in CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:67-81 [Journal]
  22. Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
    Coupling-aware high-level interconnect synthesis [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:157-164 [Journal]
  23. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang
    Minimum delay optimization for domino circuits - a coupling-aware approach. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:202-213 [Journal]
  24. Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
    Logic transformation for low-power synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:265-283 [Journal]
  25. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Noise constrained transistor sizing and power optimization for dual Vst domino logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:532-541 [Journal]
  26. Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang
    Energy-efficient skewed static logic with dual Vt: design and synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:64-70 [Journal]
  27. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
    Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:879-887 [Journal]
  28. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
    Noise-aware interconnect power optimization in domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:79-89 [Journal]

  29. Distributed cluster head election algorithm using local energy estimation. [Citation Graph (, )][DBLP]


Search in 0.040secs, Finished in 0.042secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002