Search the dblp DataBase
Nazanin Mansouri :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Shweta Shah , Nazanin Mansouri , Adrián Núñez-Aldana Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP ] CONIELECOMP, 2006, pp:38- [Conf ] Nazanin Mansouri , Ranga Vemuri Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:223-0 [Conf ] Suleyman Tosun , Nazanin Mansouri , Ercument Arvas , Mahmut T. Kandemir , Yuan Xie Reliability-Centric High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:1258-1263 [Conf ] Nazanin Mansouri , Ranga Vemuri A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. [Citation Graph (0, 0)][DBLP ] FMCAD, 1998, pp:204-221 [Conf ] Youngsik Kim , Parija Sule , Nazanin Mansouri Exploiting PSL standard assertions in a theorem-proving-based verification environment. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2005, pp:400-403 [Conf ] Deniz Dal , Nazanin Mansouri A high-level register optimization technique for minimizing leakage and dynamic power. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2007, pp:517-520 [Conf ] Shekhar Kopuri , Nazanin Mansouri Enhancing scheduling solutions through ant colony optimization. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2004, pp:257-260 [Conf ] Suleyman Tosun , Nazanin Mansouri , Mahmut T. Kandemir , Ozcan Ozturk An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors. [Citation Graph (0, 0)][DBLP ] ISCIS, 2006, pp:267-276 [Conf ] Deniz Dal , Adrian Nunez , Nazanin Mansouri Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron. [Citation Graph (0, 0)][DBLP ] ISQED, 2006, pp:165-170 [Conf ] Youngsik Kim , Shekhar Kopuri , Nazanin Mansouri Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD). [Citation Graph (0, 0)][DBLP ] ISQED, 2004, pp:110-115 [Conf ] Suleyman Tosun , Nazanin Mansouri , Ercument Arvas , Mahmut T. Kandemir , Yuan Xie , Wei-Lun Hung Reliability-Centric Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:375-380 [Conf ] Suleyman Tosun , Ozcan Ozturk , Nazanin Mansouri , Ercument Arvas , Mahmut T. Kandemir , Yuan Xie , Wei-Lun Hung An ILP Formulation for Reliability-Oriented High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:364-369 [Conf ] Suleyman Tosun , Hakduran Koc , Nazanin Mansouri Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:382-0 [Conf ] Anli He , Parija Sule , Youngsik Kim , Nazanin Mansouri Exploiting OVL standard assertions in a theorem-proving-based verification environment. [Citation Graph (0, 0)][DBLP ] Circuits, Signals, and Systems, 2004, pp:249-254 [Conf ] Nazanin Mansouri , Ranga Vemuri Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2000, v:16, n:1, pp:59-91 [Journal ] Suleyman Tosun , Nazanin Mansouri , Ercument Arvas , Mahmut T. Kandemir , Yuan Xie Reliability-Centric High-Level Synthesis [Citation Graph (0, 0)][DBLP ] CoRR, 2007, v:0, n:, pp:- [Journal ] Automated formal verification of scheduling with speculative code motions. [Citation Graph (, )][DBLP ] Determining the Optimal Number of Islands in Power Islands Synthesis. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.005secs