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Claudia Feregrino Uribe: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Miguel Morales-Sandoval, Claudia Feregrino Uribe
    A Hardware Architecture for Elliptic Curve Cryptography and Lossless Data Compression. [Citation Graph (0, 0)][DBLP]
    CONIELECOMP, 2005, pp:113-118 [Conf]
  2. Carlos Avendaño Pérez, Claudia Feregrino Uribe, Gonzalo Navarro
    Approximate Searching on Compressed Text. [Citation Graph (0, 0)][DBLP]
    CONIELECOMP, 2005, pp:258-261 [Conf]
  3. Claudia Feregrino Uribe, S. R. Jones
    Optimisation of PPMC Model for Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:120-126 [Conf]
  4. Miguel Morales-Sandoval, Claudia Feregrino Uribe
    On the Hardware Design of an Elliptic Curve Cryptosystem. [Citation Graph (0, 0)][DBLP]
    ENC, 2004, pp:64-70 [Conf]
  5. Claudia Feregrino Uribe
    High Performance PPMC Compression Algorithm. [Citation Graph (0, 0)][DBLP]
    ENC, 2003, pp:135-0 [Conf]
  6. Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido
    Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. [Citation Graph (0, 0)][DBLP]
    ICCSA (3), 2006, pp:456-465 [Conf]
  7. Roshan Duraisamy, Zoran A. Salcic, Miguel Morales-Sandoval, Claudia Feregrino Uribe
    A Fast Elliptic Curve Based Key Agreement Protocol-on-Chip (PoC) for Securing Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:154-161 [Conf]

  8. A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. [Citation Graph (, )][DBLP]

  9. FPGA-Based Architecture for Computing Testors. [Citation Graph (, )][DBLP]

  10. A Versatile Linear Insertion Sorter Based on a FIFO Scheme. [Citation Graph (, )][DBLP]

  11. Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard. [Citation Graph (, )][DBLP]

  12. FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. [Citation Graph (, )][DBLP]

  13. A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. [Citation Graph (, )][DBLP]

  14. FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. [Citation Graph (, )][DBLP]

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