
Search the dblp DataBase
Claudia Feregrino Uribe:
[Publications]
[Author Rank by year]
[Coauthors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
 Miguel MoralesSandoval, Claudia Feregrino Uribe
A Hardware Architecture for Elliptic Curve Cryptography and Lossless Data Compression. [Citation Graph (0, 0)][DBLP] CONIELECOMP, 2005, pp:113118 [Conf]
 Carlos Avendaño Pérez, Claudia Feregrino Uribe, Gonzalo Navarro
Approximate Searching on Compressed Text. [Citation Graph (0, 0)][DBLP] CONIELECOMP, 2005, pp:258261 [Conf]
 Claudia Feregrino Uribe, S. R. Jones
Optimisation of PPMC Model for Hardware Implementation. [Citation Graph (0, 0)][DBLP] DSD, 2001, pp:120126 [Conf]
 Miguel MoralesSandoval, Claudia Feregrino Uribe
On the Hardware Design of an Elliptic Curve Cryptosystem. [Citation Graph (0, 0)][DBLP] ENC, 2004, pp:6470 [Conf]
 Claudia Feregrino Uribe
High Performance PPMC Compression Algorithm. [Citation Graph (0, 0)][DBLP] ENC, 2003, pp:1350 [Conf]
 Ignacio AlgredoBadillo, Claudia Feregrino Uribe, René Cumplido
Design and Implementation of an FPGABased 1.452Gbps Nonpipelined AES Architecture. [Citation Graph (0, 0)][DBLP] ICCSA (3), 2006, pp:456465 [Conf]
 Roshan Duraisamy, Zoran A. Salcic, Miguel MoralesSandoval, Claudia Feregrino Uribe
A Fast Elliptic Curve Based Key Agreement ProtocolonChip (PoC) for Securing Networked Embedded Systems. [Citation Graph (0, 0)][DBLP] RTCSA, 2006, pp:154161 [Conf]
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. [Citation Graph (, )][DBLP]
FPGABased Architecture for Computing Testors. [Citation Graph (, )][DBLP]
A Versatile Linear Insertion Sorter Based on a FIFO Scheme. [Citation Graph (, )][DBLP]
Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard. [Citation Graph (, )][DBLP]
FPGA Implementation and Performance Evaluation of AESCCM Cores for Wireless Networks. [Citation Graph (, )][DBLP]
A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. [Citation Graph (, )][DBLP]
FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. [Citation Graph (, )][DBLP]
Search in 0.030secs, Finished in 0.032secs
