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Teruo Tanaka:
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Publications of Author
- Naoki Hamanaka, Junji Nakagoshi, Teruo Tanaka
Reducing Network Hardware Quantity by Employing Multi-Processor Cluster Structure in Distributed Memory Parallel Processors. [Citation Graph (0, 0)][DBLP] CONPAR, 1992, pp:25-30 [Conf]
- Frederico B. Maciel, Nobutoshi Sagawa, Teruo Tanaka
Dynamic Gateways: A Novel Approach to Improve Networking Performance and Availability on Parallel Servers. [Citation Graph (0, 0)][DBLP] HPCN Europe, 1998, pp:678-687 [Conf]
- Katsuyoshi Kitai, Tadaaki Isobe, Tadayuki Sakakibara, Shigeko Yazawa, Yoshiko Tamaki, Teruo Tanaka, Kouichi Ishii
Distributed storage control unit for the Hitachi S-3800 multivector supercomputer. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1994, pp:1-10 [Conf]
- Katsuyoshi Kitai, Tadaaki Isobe, Yoshikazu Tanaka, Yoshiko Tamaki, Masakazu Fukagawa, Teruo Tanaka, Yasuhiro Inagami
Parallel Processing Architecture for the Hitachi S-3800 Shared-Memory Vector Multiprocessor. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:288-297 [Conf]
- Tadayuki Sakakibara, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Yazawa, Teruo Tanaka, Yasuhiro Inagami, Yoshiko Tamaki
Scalable Parallel Memory Architecture with a Skew Scheme. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:157-166 [Conf]
- Yoshiko Yasuda, Hiroaki Fujii, Hideya Akashi, Yasuhiro Inagami, Teruo Tanaka, Junji Nakagoshi, Hideo Wada, Tsutomu Sumimoto
Deadlock-Free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and Its Implementation for the Hitachi SR2201. [Citation Graph (0, 0)][DBLP] IPPS, 1997, pp:346-352 [Conf]
- Teruo Tanaka, Takahiro Katagiri, Toshitsugu Yuba
d-Spline Based Incremental Parameter Estimation in Automatic Performance Tuning. [Citation Graph (0, 0)][DBLP] PARA, 2006, pp:986-995 [Conf]
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