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Igor Z. Milovanovic:
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Publications of Author
- Emina I. Milovanovic, Igor Z. Milovanovic, Mile K. Stojcev
Matrix Inversion Algorithm for Linear Array Processor. [Citation Graph (0, 0)][DBLP] CONPAR, 1992, pp:367-372 [Conf]
- Mile K. Stojcev, Igor Z. Milovanovic, Emina I. Milovanovic, G. S. Jovanovic
Real-Number Codes for Fault-Tolerant Matrix Inversion on Processor Arrays. [Citation Graph (0, 0)][DBLP] CONPAR, 1992, pp:821-822 [Conf]
- Mile K. Stojcev, Emina I. Milovanovic, Milan D. Mihajlovic, Igor Z. Milovanovic
Parallel Algorithm for Inverting Tridiagonal Matrix on Linear Processor Array. [Citation Graph (0, 0)][DBLP] CONPAR, 1994, pp:229-240 [Conf]
- Igor Z. Milovanovic, Emina I. Milovanovic, B. M. Randjelovic
Computing Transitive Closure Problem on Linear Systolic Array. [Citation Graph (0, 0)][DBLP] NAA, 2004, pp:416-423 [Conf]
- Emina I. Milovanovic, Igor Z. Milovanovic, Mile K. Stojcev, Milan D. Mihajlovic
An Optimal Algorithm for Gaussian Elimination of Band Matrices on a MIMD System. [Citation Graph (0, 0)][DBLP] Computers and Artificial Intelligence, 1996, v:15, n:5, pp:- [Journal]
- Emina I. Milovanovic, I. Z. Milentijevic, Igor Z. Milovanovic
Designing of Processor-Time Optimal Hexagonal Systolic Array for Matrix Multiplication. [Citation Graph (0, 0)][DBLP] Computers and Artificial Intelligence, 1997, v:16, n:1, pp:- [Journal]
- Igor Z. Milovanovic, Emina I. Milovanovic, Mile K. Stojcev
An optimal algoPaulrajrithm for Gaussian elimination of band matrices on an MIMD computer. [Citation Graph (0, 0)][DBLP] Parallel Computing, 1990, v:15, n:1-3, pp:133-145 [Journal]
- Mile K. Stojcev, Emina I. Milovanovic, Igor Z. Milovanovic
An algorithm for multiplication of concatenated matrices. [Citation Graph (0, 0)][DBLP] Parallel Computing, 1990, v:13, n:2, pp:211-223 [Journal]
- Emina I. Milovanovic, Igor Z. Milovanovic, Mile K. Stojcev
Solving Tridiagonal Linear Systems on MIMD Computers. [Citation Graph (0, 0)][DBLP] Parallel Processing Letters, 1994, v:4, n:, pp:53-64 [Journal]
- Emina I. Milovanovic, Igor Z. Milovanovic, M. P. Bekakos, I. N. Tselepis
Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform. [Citation Graph (0, 0)][DBLP] The Journal of Supercomputing, 2007, v:40, n:1, pp:49-66 [Journal]
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