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Mario Nemirovsky: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mauricio J. Serrano, Wayne Yamamoto, Roger C. Wood, Mario Nemirovsky
    A Model for Performance Estimation in a Multistreamed Superscalar Processor. [Citation Graph (0, 0)][DBLP]
    Computer Performance Evaluation, 1994, pp:213-230 [Conf]
  2. Wayne Yamamoto, Mauricio J. Serrano, Adam R. Talcott, Roger C. Wood, Mario Nemirovsky
    Performance Estimation of Multistreamed, Supersealar Processors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:195-204 [Conf]
  3. Adam R. Talcott, Wayne Yamamoto, Mauricio J. Serrano, Roger C. Wood, Mario Nemirovsky
    The Impact of Unresolved Branches on Branch Prediction Scheme Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:12-21 [Conf]
  4. Mario Nemirovsky, Forrest Brewer, Roger C. Wood
    DISC: Dynamic Instruction Stream Computer. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:163-171 [Conf]
  5. Rafael R. dos Santos, Tatiana G. S. dos Santos, Maurício L. Pilla, Philippe Olivier Alexandre Navaux, Sergio Bampi, Mario Nemirovsky
    Complex Branch Profiling for Dynamic Conditional Execution. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2003, pp:28-35 [Conf]
  6. Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero
    Architectural impact of stateful networking applications. [Citation Graph (0, 0)][DBLP]
    ANCS, 2005, pp:11-18 [Conf]
  7. Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero
    The impact of traffic aggregation on the memory performance of networking applications. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:57-62 [Journal]

  8. Characterizing the resource-sharing levels in the UltraSPARC T2 processor. [Citation Graph (, )][DBLP]

  9. Thread to strand binding of parallel network applications in massive multi-threaded systems. [Citation Graph (, )][DBLP]

  10. Measuring Operating System Overhead on CMT Processors. [Citation Graph (, )][DBLP]

  11. MultiLayer processing - an execution model for parallel stateful packet processing. [Citation Graph (, )][DBLP]

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