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Peixin Zhong: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhaohui Huang, Peixin Zhong
    Adaptive Analog-to-Digital Converter Platform for Mixed-Signal System-on-Chip. [Citation Graph (0, 0)][DBLP]
    ESA, 2005, pp:69-73 [Conf]
  2. Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi
    Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:194-199 [Conf]
  3. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Accelerating Boolean Satisfiability with Configurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:186-195 [Conf]
  4. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Solving Boolean Satisfiability with Dynamic Hardware Configurations. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:326-335 [Conf]
  5. Jinwen Xi, Peixin Zhong
    A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:341-344 [Conf]
  6. Zhaohui Huang, Peixin Zhong
    An Architectural Power Estimator for Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:397-400 [Conf]
  7. Jinwen Xi, Peixin Zhong
    Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:502-504 [Conf]
  8. Jinwen Xi, Peixin Zhong
    Fast Energy Estimation of Multi-processor System-on-Chip with Energy Macro-Models for Embedded Microprocessors. [Citation Graph (0, 0)][DBLP]
    MSV, 2005, pp:107-111 [Conf]
  9. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Using configurable computing to accelerate Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:861-868 [Journal]

  10. A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models. [Citation Graph (, )][DBLP]

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