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Camel Tanougast: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber
    FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:606-610 [Conf]
  2. Michael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber
    Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:386-390 [Conf]
  3. Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber
    FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1027-1031 [Conf]
  4. Camel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber
    Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:178- [Conf]
  5. Camel Tanougast, Yves Berviller, Serge Weber
    Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:959-965 [Conf]
  6. Philippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber
    Hardware Partitioning Software for Dynamically Reconfigurable SoC Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:106-111 [Conf]
  7. Camel Tanougast, Yves Berviller, Christian Mannino, Hassan Rabah, Michael Janiaut, Serge Weber
    SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:157-163 [Conf]
  8. Hassan Rabah, Hervé Mathias, Serge Weber, E. Mozef, Camel Tanougast
    Linear array processors with multiple access modes memory for real-time image processing. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 2003, v:9, n:3, pp:205-213 [Journal]
  9. Camel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber, Hassan Rabah
    Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:3, pp:115-130 [Journal]
  10. S. Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber
    A Dynamic Communication Structure for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:98-105 [Conf]

  11. A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systems. [Citation Graph (, )][DBLP]


  12. VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher. [Citation Graph (, )][DBLP]


  13. CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  14. A new deadlock-free fault-tolerant routing algorithm for NoC interconnections. [Citation Graph (, )][DBLP]


  15. A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems. [Citation Graph (, )][DBLP]


  16. AES Embedded Hardware Implementation. [Citation Graph (, )][DBLP]


  17. An Fpga implementation of the HME self-synchronizing stream cipher for Enhanced security and performance. [Citation Graph (, )][DBLP]


  18. A New Self-Managing Hardware Design Approach for FPGA-based Reconfigurable Systems. [Citation Graph (, )][DBLP]


  19. A framework of architectural synthesis for dynamically reconfigurable FPGAs. [Citation Graph (, )][DBLP]


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