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Eriko Nurvitadhi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Kim
    A Comparative Study of Dynamic Voltage Scaling Techniques for Low-Power Video Decoding. [Citation Graph (0, 0)][DBLP]
    Embedded Systems and Applications, 2003, pp:292-298 [Conf]
  2. Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu
    Design, implementation, and verification of active cache emulator (ACE). [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:63-72 [Conf]
  3. Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu
    Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:12-20 [Conf]
  4. Ben Lee, Eriko Nurvitadhi, Reshma Dixit, Chansu Yu, Myungchul Kim
    Dynamic voltage scaling techniques for power efficient video decoding. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:10-11, pp:633-652 [Journal]
  5. Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
    TRUSS: A Reliable, Scalable Server Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:6, pp:51-59 [Journal]
  6. Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
    PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]

  7. Automatic multithreaded pipeline synthesis from transactional datapath specifications. [Citation Graph (, )][DBLP]


  8. Automatic pipelining from transactional datapath specifications. [Citation Graph (, )][DBLP]


  9. A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. [Citation Graph (, )][DBLP]


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