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Pasquale Corsonello: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pasquale Corsonello, Stefania Perri, Vitit Kantabutra
    Area- and Power-Reduced Standard-Cell Spanning Tree Adders. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:343-352 [Conf]
  2. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
    Designing High-Speed Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1394-1399 [Conf]
  3. Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo
    Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:661-669 [Conf]
  4. Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello
    Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:13-18 [Conf]
  5. Marco Lanuzza, Martin Margala, Pasquale Corsonello
    Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:161-166 [Conf]
  6. Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
    VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:195-204 [Conf]
  7. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
    Fast Low-Power 64-Bit Modular Hybrid Adder. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:609-617 [Conf]
  8. Pasquale Corsonello, Giandomenico Spezzano, G. Staino, Domenico Talia
    Efficient Implementation of Cellular Algorithms on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    PDP, 2002, pp:211-218 [Conf]
  9. Pasquale Corsonello, Stefania Perri
    Efficient Reconfigurable Manchester Adders for Low-power Media Processing. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:1, pp:57-64 [Journal]
  10. Pasquale Corsonello, Stefania Perri, G. Staino, Marco Lanuzza, Giuseppe Cocorullo
    Low bit rate image compression core for onboard space applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:1, pp:114-128 [Journal]
  11. Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo
    Variable precision arithmetic circuits for FPGA-based multimedia processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:995-999 [Journal]
  12. Pasquale Corsonello, Stefania Perri, Paolo Zicari, Giuseppe Cocorullo
    Microprocessor-based FPGA implementation of SPIHT image compression subsystems. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:6, pp:299-305 [Journal]
  13. Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo
    A high-performance fully reconfigurable FPGA-based 2D convolution processor. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:8-9, pp:381-391 [Journal]
  14. Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
    Leakage energy reduction techniques in deep submicron cache memories: a comparative study. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  15. Pasquale Corsonello, Stefania Perri, Martin Margala
    An integrated countermeasure against differential power analysis for secure smart-cards. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  16. Marco Lanuzza, Stefania Perri, Pasquale Corsonello
    MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:159-168 [Conf]
  17. Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
    Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1238-1249 [Journal]
  18. Pasquale Corsonello, Stefania Perri, G. Cororullo
    Area-time-power tradeoff in cellular arrays VLSI implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:614-624 [Journal]
  19. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
    VLSI circuits for low-power high-speed asynchronous addition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:608-613 [Journal]
  20. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
    A high-speed energy-efficient 64-bit reconfigurable binary adder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:939-943 [Journal]

  21. An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector. [Citation Graph (, )][DBLP]


  22. Design and Implementation of a 90nm Low bit-rate Image Compression Core. [Citation Graph (, )][DBLP]


  23. New performance/power/area efficient, reliable full adder design. [Citation Graph (, )][DBLP]


  24. Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. [Citation Graph (, )][DBLP]


  25. A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. [Citation Graph (, )][DBLP]


  26. Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. [Citation Graph (, )][DBLP]


  27. A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. [Citation Graph (, )][DBLP]


  28. An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. [Citation Graph (, )][DBLP]


  29. Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. [Citation Graph (, )][DBLP]


  30. Quad-Port Memory Blocks in Radiation-Tolerant FPGAs: An Application for Image Processing Systems. [Citation Graph (, )][DBLP]


  31. Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. [Citation Graph (, )][DBLP]


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