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Dilip K. Banerji: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gary Gréwal, S. Coros, D. Banerji, Andrew Morton
    Comparing a Genetic Algorithm Penalty Function and Repair Heuristic in the DSP Application Domain. [Citation Graph (0, 0)][DBLP]
    Artificial Intelligence and Applications, 2006, pp:31-39 [Conf]
  2. Peng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji
    A Fast Hierarchical Approach to FPGA Placement. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:497-503 [Conf]
  3. Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji
    An ILP-based approach to code generation. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:103-118 [Conf]
  4. Wei Li, Dilip K. Banerji
    Routability Prediction for Hierarchical FPGAs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:256-259 [Conf]
  5. Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji
    An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:581-586 [Conf]
  6. Zhibin Dai, Dilip K. Banerji
    Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:85-90 [Conf]
  7. Gary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji
    Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:855-862 [Conf]
  8. J. Shu, Thomas Charles Wilson, Dilip K. Banerji
    Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:73-76 [Conf]
  9. Thomas Charles Wilson, Nilanjan Mukherjee, M. K. Garg, Dilip K. Banerji
    An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:192-197 [Conf]
  10. Gary Gréwal, S. Coros, D. Banerji, Andrew Morton
    Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic. [Citation Graph (0, 0)][DBLP]
    Appl. Intell., 2007, v:26, n:1, pp:53-67 [Journal]
  11. M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders
    A Semantic Approach for Modular Synthesis of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1988, v:27, n:1, pp:1-7 [Journal]
  12. M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia
    Allocation of multiport memories in data path synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:536-540 [Journal]
  13. Shouvik Chowdhury, Gary William Grewal, Dilip K. Banerji
    Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:1223-1227 [Conf]

  14. Near-linear wirelength estimation for FPGA placement. [Citation Graph (, )][DBLP]

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